Line data Source code
1 : /* This is the VM SBPF interpreter core. The caller unpacks the VM
2 : state and then just lets execution continue into this (or jumps to
3 : interp_exec) to start running. The VM will run until it halts or
4 : faults. On normal termination, it will branch to interp_halt to
5 : exit. Each fault has its own exit label to allow the caller to
6 : handle individually. */
7 :
8 : /* FIXME: SIGILLS FOR VARIOUS THINGS THAT HAVE UNNECESSARY BITS IN IMM
9 : SET? (LIKE WIDE SHIFTS?) */
10 :
11 0 : # if defined(__GNUC__) /* -Wpedantic rejects labels as values and rejects goto *expr */
12 0 : # pragma GCC diagnostic push
13 0 : # pragma GCC diagnostic ignored "-Wpedantic"
14 0 : # endif
15 :
16 0 : # if defined(__clang__) /* Clang is differently picky about labels as values and goto *expr */
17 0 : # pragma clang diagnostic push
18 0 : # pragma clang diagnostic ignored "-Wpedantic"
19 0 : # pragma clang diagnostic ignored "-Wgnu-label-as-value"
20 0 : # endif
21 :
22 : /* Include the jump table */
23 :
24 11295 : # include "fd_vm_interp_jump_table.c"
25 :
26 : /* Update the jump table based on SBPF version */
27 :
28 0 : ulong sbpf_version = vm->sbpf_version;
29 :
30 : /* Unpack the VM state */
31 :
32 0 : ulong pc = vm->pc;
33 0 : ulong ic = vm->ic;
34 0 : ulong cu = vm->cu;
35 0 : ulong frame_cnt = vm->frame_cnt;
36 :
37 0 : void const * const * const version_interp_jump_table = interp_jump_table[ sbpf_version ];
38 :
39 : /* FD_VM_INTERP_INSTR_EXEC loads the first word of the instruction at
40 : pc, parses it, fetches the associated register values and then
41 : jumps to the code that executes the instruction. On normal
42 : instruction execution, the pc will be updated and
43 : FD_VM_INTERP_INSTR_EXEC will be invoked again to do the next
44 : instruction. After a normal halt, this will branch to interp_halt.
45 : Otherwise, it will branch to the appropriate normal termination. */
46 :
47 0 : ulong instr;
48 0 : ulong opcode;
49 0 : ulong dst;
50 0 : ulong src;
51 0 : ulong offset; /* offset is 16-bit but always sign extended, so we handle cast once */
52 0 : uint imm;
53 0 : ulong reg_dst;
54 0 : ulong reg_src;
55 :
56 : /* These mimic the exact Rust semantics for wrapping_shl and wrapping_shr. */
57 :
58 : /* u64::wrapping_shl: a.unchecked_shl(b & (64 - 1))
59 :
60 : https://doc.rust-lang.org/std/primitive.u64.html#method.wrapping_shl
61 : */
62 465 : #define FD_RUST_ULONG_WRAPPING_SHL( a, b ) ((a) << ( (b) & ( 63 ) ))
63 :
64 : /* u64::wrapping_shr: a.unchecked_shr(b & (64 - 1))
65 :
66 : https://doc.rust-lang.org/std/primitive.u64.html#method.wrapping_shr
67 : */
68 21 : #define FD_RUST_ULONG_WRAPPING_SHR( a, b ) ((a) >> ( (b) & ( 63 ) ))
69 :
70 : /* u32::wrapping_shl: a.unchecked_shl(b & (32 - 1))
71 :
72 : https://doc.rust-lang.org/std/primitive.u32.html#method.wrapping_shl
73 : */
74 900 : #define FD_RUST_UINT_WRAPPING_SHL( a, b ) ((a) << ( (b) & ( 31 ) ))
75 :
76 : /* u32::wrapping_shr: a.unchecked_shr(b & (32 - 1))
77 :
78 : https://doc.rust-lang.org/std/primitive.u32.html#method.wrapping_shr
79 : */
80 18 : #define FD_RUST_UINT_WRAPPING_SHR( a, b ) ((a) >> ( (b) & ( 31 ) ))
81 :
82 : /* i32::wrapping_shr: a.unchecked_shr(b & (32 - 1))
83 :
84 : https://doc.rust-lang.org/std/primitive.i32.html#method.wrapping_shr
85 : */
86 243 : #define FD_RUST_INT_WRAPPING_SHR( a, b ) ((a) >> ( (b) & ( 31 ) ))
87 :
88 : /* i64::wrapping_shr: a.unchecked_shr(b & (64 - 1))
89 :
90 : https://doc.rust-lang.org/std/primitive.i64.html#method.wrapping_shr
91 : */
92 228 : #define FD_RUST_LONG_WRAPPING_SHR( a, b ) ((a) >> ( (b) & ( 63 ) ))
93 :
94 :
95 0 : # define FD_VM_INTERP_INSTR_EXEC \
96 405720 : if( FD_UNLIKELY( pc>=text_cnt ) ) goto sigtext; /* Note: untaken branches don't consume BTB */ \
97 405720 : instr = text[ pc ]; /* Guaranteed in-bounds */ \
98 405585 : opcode = fd_vm_instr_opcode( instr ); /* in [0,256) even if malformed */ \
99 405585 : dst = fd_vm_instr_dst ( instr ); /* in [0, 16) even if malformed */ \
100 405585 : src = fd_vm_instr_src ( instr ); /* in [0, 16) even if malformed */ \
101 405585 : offset = fd_vm_instr_offset( instr ); /* in [-2^15,2^15) even if malformed */ \
102 405585 : imm = fd_vm_instr_imm ( instr ); /* in [0,2^32) even if malformed */ \
103 405585 : reg_dst = reg[ dst ]; /* Guaranteed in-bounds */ \
104 405585 : reg_src = reg[ src ]; /* Guaranteed in-bounds */ \
105 405585 : goto *version_interp_jump_table[ opcode ] /* Guaranteed in-bounds */
106 :
107 : /* FD_VM_INTERP_SYSCALL_EXEC
108 : (macro to handle the logic of 0x85 pre- and post- SIMD-0178: static syscalls)
109 :
110 : Setup.
111 : Update the vm with the current vm execution state for the
112 : syscall. Note that BRANCH_BEGIN has pc at the syscall and
113 : already updated ic and cu to reflect all instructions up to
114 : and including the syscall instruction itself.
115 :
116 : Execution.
117 : Do the syscall. We use ret reduce the risk of the syscall
118 : accidentally modifying other registers (note however since a
119 : syscall has the vm handle it still do arbitrary modifications
120 : to the vm state) and the risk of a pointer escape on reg from
121 : inhibiting compiler optimizations (this risk is likely low in
122 : as this is the only point in the whole interpreter core that
123 : calls outside this translation unit).
124 : At this point, vm->cu is positive.
125 :
126 : Error handling.
127 : If we trust syscall implementations to handle the vm state
128 : correctly, the below could be implemented as unpacking the vm
129 : state and jumping to sigsys on error. But we provide some
130 : extra protection to make various strong guarantees:
131 :
132 : - We do not let the syscall modify pc currently as nothing
133 : requires this and it reduces risk of a syscall bug mucking
134 : up the interpreter. If there ever was a syscall that
135 : needed to modify the pc (e.g. a syscall that has execution
136 : resume from a different location than the instruction
137 : following the syscall), do "pc = vm->pc" below.
138 :
139 : - We do not let the syscall modify ic currently as nothing
140 : requires this and it keeps the ic precise. If a future
141 : syscall needs this, do "ic = vm->ic" below.
142 :
143 : - We do not let the syscall increase cu as nothing requires
144 : this and it guarantees the interpreter will halt in a
145 : reasonable finite amount of time. If a future syscall
146 : needs this, do "cu = vm->cu" below.
147 :
148 : - A syscall that returns SIGCOST is always treated as though
149 : it also zerod cu.
150 :
151 : At this point, vm->cu is whatever the syscall tried to set
152 : and cu is positive.
153 :
154 : Exit
155 : At this point, cu is positive and err is clear.
156 : */
157 :
158 0 : # define FD_VM_INTERP_SYSCALL_EXEC_DUMP \
159 : /* Dumping for debugging purposes */ \
160 12 : if( FD_UNLIKELY( vm->dump_syscall_to_pb ) ) { \
161 0 : fd_dump_vm_syscall_to_protobuf( vm, syscall->name ); \
162 0 : }
163 :
164 0 : # define FD_VM_INTERP_SYSCALL_EXEC \
165 : /* Setup */ \
166 12 : vm->pc = pc; \
167 12 : vm->ic = ic; \
168 12 : vm->cu = cu; \
169 12 : vm->frame_cnt = frame_cnt; \
170 12 : FD_VM_INTERP_SYSCALL_EXEC_DUMP \
171 : /* Execution */ \
172 12 : ulong ret[1]; \
173 12 : err = syscall->func( vm, reg[1], reg[2], reg[3], reg[4], reg[5], ret ); \
174 12 : reg[0] = ret[0]; \
175 : /* Error handling */ \
176 12 : ulong cu_req = vm->cu; \
177 12 : cu = fd_ulong_min( cu_req, cu ); \
178 12 : if( FD_UNLIKELY( err ) ) { \
179 0 : if( err==FD_VM_SYSCALL_ERR_COMPUTE_BUDGET_EXCEEDED ) cu = 0UL; /* cmov */ \
180 0 : FD_VM_TEST_ERR_EXISTS( vm ); \
181 0 : goto sigsyscall; \
182 0 : } \
183 : /* Exit */
184 :
185 :
186 : /* FD_VM_INTERP_INSTR_BEGIN / FD_VM_INTERP_INSTR_END bracket opcode's
187 : implementation for an opcode that does not branch. On entry, the
188 : instruction word has been unpacked into dst / src / offset / imm
189 : and reg[dst] / reg[src] has been prefetched into reg_dst / reg_src. */
190 :
191 252831 : # define FD_VM_INTERP_INSTR_BEGIN(opcode) interp_##opcode:
192 :
193 : # ifndef FD_VM_INTERP_EXE_TRACING_ENABLED /* Non-tracing path only, ~0.3% faster in some benchmarks, slower in others but more code footprint */
194 252435 : # define FD_VM_INTERP_INSTR_END pc++; FD_VM_INTERP_INSTR_EXEC
195 : # else /* Use this version when tracing or optimizing code footprint */
196 0 : # define FD_VM_INTERP_INSTR_END pc++; goto interp_exec
197 : # endif
198 :
199 : /* Instead of doing a lot of compute budget calcs and tests every
200 : instruction, we note that the program counter increases
201 : monotonically after a branch (or a program start) until the next
202 : branch (or program termination). We save the program counter of
203 : the start of such a segment in pc0. Whenever we encounter a branch
204 : (or a program termination) at pc, we know we processed pc-pc0+1
205 : text words (including the text word for the branch instruction
206 : itself as all branch instructions are single word).
207 :
208 : Each instruction costs 1 cu (syscalls can cost extra on top of
209 : this that is accounted separately in CALL_IMM below). Since there
210 : could have been multiword instructions in this segment, at start of
211 : such a segment, we zero out the accumulator ic_correction and have
212 : every multiword instruction in the segment accumulate the number of
213 : extra text words it has to this variable. (Sigh ... it would be a
214 : lot simpler to bill based on text words processed but this would be
215 : very difficult to make this protocol change at this point.)
216 :
217 : When we encounter a branch at pc, the number of instructions
218 : processed (and thus the number of compute units to bill for that
219 : segment) is thus:
220 :
221 : pc - pc0 + 1 - ic_correction
222 :
223 : IMPORTANT SAFETY TIP! This implies the worst case interval before
224 : checking the cu budget is the worst case text_cnt. But since all
225 : such instructions are cheap 1 cu instructions and processed fast
226 : and text max is limited in size, this should be acceptable in
227 : practice. FIXME: DOUBLE CHECK THE MATH ABOVE AGAINST PROTOCOL
228 : LIMITS. */
229 :
230 0 : ulong pc0 = pc;
231 0 : ulong ic_correction = 0UL;
232 :
233 0 : # define FD_VM_INTERP_BRANCH_BEGIN(opcode) \
234 151578 : interp_##opcode: \
235 : /* Bill linear text segment and this branch instruction as per the above */ \
236 151578 : ic_correction = pc - pc0 + 1UL - ic_correction; \
237 151578 : ic += ic_correction; \
238 151578 : if( FD_UNLIKELY( ic_correction>cu ) ) goto sigcost; /* Note: untaken branches don't consume BTB */ \
239 151578 : cu -= ic_correction; \
240 : /* At this point, cu>=0 */ \
241 150771 : ic_correction = 0UL;
242 :
243 : /* FIXME: debatable if it is better to do pc++ here or have the
244 : instruction implementations do it in their code path. */
245 :
246 : # ifndef FD_VM_INTERP_EXE_TRACING_ENABLED /* Non-tracing path only, ~4% faster in some benchmarks, slower in others but more code footprint */
247 : # define FD_VM_INTERP_BRANCH_END \
248 141960 : pc++; \
249 141960 : pc0 = pc; /* Start a new linear segment */ \
250 141990 : FD_VM_INTERP_INSTR_EXEC
251 : # else /* Use this version when tracing or optimizing code footprint */
252 : # define FD_VM_INTERP_BRANCH_END \
253 0 : pc++; \
254 0 : pc0 = pc; /* Start a new linear segment */ \
255 : /* FIXME: TEST sigsplit HERE */ \
256 0 : goto interp_exec
257 : # endif
258 :
259 : /* FD_VM_INTERP_STACK_PUSH pushes reg[6:9] onto the shadow stack and
260 : advances reg[10] to a new user stack frame. If there are no more
261 : stack frames available, will do a SIGSTACK. */
262 :
263 : /* FIXME: double check faulting is desired on stack overflow. */
264 :
265 : /* FIXME: a pre-belt-sanding FIXME implied the TLB should be updated
266 : to prevent byte code from accessing the stack outside its current
267 : stack frame. But this would break the common practice of a
268 : function passing a pointer to something on its stack into a
269 : function that it calls:
270 :
271 : void foo( ... ) {
272 : ...
273 : int ret;
274 : bar( &ret );
275 : ...
276 : }
277 :
278 : So this probably shouldn't be done. But, if it is in fact
279 : necessary, the TLB updates would be here and in pop. */
280 :
281 : /* FIXME: unvalidated code mucking with r10 */
282 :
283 0 : # define FD_VM_INTERP_STACK_PUSH \
284 255 : shadow[ frame_cnt ].r6 = reg[6]; \
285 255 : shadow[ frame_cnt ].r7 = reg[7]; \
286 255 : shadow[ frame_cnt ].r8 = reg[8]; \
287 255 : shadow[ frame_cnt ].r9 = reg[9]; \
288 255 : shadow[ frame_cnt ].r10 = reg[10]; \
289 255 : shadow[ frame_cnt ].pc = pc; \
290 255 : if( FD_UNLIKELY( ++frame_cnt>=frame_max ) ) goto sigstack; /* Note: untaken branches don't consume BTB */ \
291 255 : reg[10] += vm->stack_frame_sz * vm->stack_push_frame_count; \
292 : /* We subtract the heap cost in the BPF loader */
293 :
294 0 : goto interp_exec; /* Silly but to avoid unused label warning in some configurations */
295 11295 : interp_exec:
296 :
297 : # ifdef FD_VM_INTERP_EXE_TRACING_ENABLED
298 : /* Note: when tracing or optimizing for code footprint, all
299 : instruction execution starts here such that this is only point
300 : where exe tracing diagnostics are needed. */
301 0 : if( FD_UNLIKELY( pc>=text_cnt ) ) goto sigtext;
302 0 : fd_vm_trace_event_exe( vm->trace, pc, ic + ( pc - pc0 - ic_correction ), cu, reg, vm->text + pc, vm->text_cnt - pc, ic_correction, frame_cnt );
303 0 : # endif
304 :
305 11295 : FD_VM_INTERP_INSTR_EXEC;
306 :
307 : /* 0x00 - 0x0f ******************************************************/
308 :
309 11295 : FD_VM_INTERP_INSTR_BEGIN(0x04) /* FD_SBPF_OP_ADD_IMM */
310 36 : reg[ dst ] = (ulong)(uint)( (int)reg_dst + (int)imm );
311 36 : FD_VM_INTERP_INSTR_END;
312 :
313 45 : FD_VM_INTERP_INSTR_BEGIN(0x04depr) /* FD_SBPF_OP_ADD_IMM deprecated SIMD-0174 */
314 45 : reg[ dst ] = (ulong)(long)( (int)reg_dst + (int)imm );
315 45 : FD_VM_INTERP_INSTR_END;
316 :
317 642 : FD_VM_INTERP_BRANCH_BEGIN(0x05) /* FD_SBPF_OP_JA */
318 636 : pc += offset;
319 636 : FD_VM_INTERP_BRANCH_END;
320 :
321 30108 : FD_VM_INTERP_INSTR_BEGIN(0x07) /* FD_SBPF_OP_ADD64_IMM */
322 30108 : reg[ dst ] = reg_dst + (ulong)(long)(int)imm;
323 30108 : FD_VM_INTERP_INSTR_END;
324 :
325 33 : FD_VM_INTERP_INSTR_BEGIN(0x0c) /* FD_SBPF_OP_ADD_REG */
326 33 : reg[ dst ] = (ulong)(uint)( (int)reg_dst + (int)reg_src );
327 33 : FD_VM_INTERP_INSTR_END;
328 :
329 39 : FD_VM_INTERP_INSTR_BEGIN(0x0cdepr) /* FD_SBPF_OP_ADD_REG deprecated SIMD-0174 */
330 39 : reg[ dst ] = (ulong)(long)( (int)reg_dst + (int)reg_src );
331 39 : FD_VM_INTERP_INSTR_END;
332 :
333 78 : FD_VM_INTERP_INSTR_BEGIN(0x0f) /* FD_SBPF_OP_ADD64_REG */
334 78 : reg[ dst ] = reg_dst + reg_src;
335 78 : FD_VM_INTERP_INSTR_END;
336 :
337 : /* 0x10 - 0x1f ******************************************************/
338 :
339 36 : FD_VM_INTERP_INSTR_BEGIN(0x14) /* FD_SBPF_OP_SUB_IMM */
340 36 : reg[ dst ] = (ulong)(uint)( (int)imm - (int)reg_dst );
341 36 : FD_VM_INTERP_INSTR_END;
342 :
343 39 : FD_VM_INTERP_INSTR_BEGIN(0x14depr) /* FD_SBPF_OP_SUB_IMM deprecated SIMD-0174 */
344 39 : reg[ dst ] = (ulong)(long)( (int)reg_dst - (int)imm );
345 39 : FD_VM_INTERP_INSTR_END;
346 :
347 1254 : FD_VM_INTERP_BRANCH_BEGIN(0x15) /* FD_SBPF_OP_JEQ_IMM */
348 1242 : pc += fd_ulong_if( reg_dst==(ulong)(long)(int)imm, offset, 0UL );
349 1242 : FD_VM_INTERP_BRANCH_END;
350 :
351 33 : FD_VM_INTERP_INSTR_BEGIN(0x17) /* FD_SBPF_OP_SUB64_IMM */
352 33 : reg[ dst ] = (ulong)(long)(int)imm - reg_dst;
353 33 : FD_VM_INTERP_INSTR_END;
354 :
355 36 : FD_VM_INTERP_INSTR_BEGIN(0x17depr) /* FD_SBPF_OP_SUB64_IMM deprecated SIMD-0174 */
356 36 : reg[ dst ] = reg_dst - (ulong)(long)(int)imm;
357 36 : FD_VM_INTERP_INSTR_END;
358 :
359 144 : FD_VM_INTERP_INSTR_BEGIN(0x18) /* FD_SBPF_OP_LDQ */
360 144 : pc++;
361 144 : ic_correction++;
362 : /* No need to check pc because it's already checked during validation.
363 : if( FD_UNLIKELY( pc>=text_cnt ) ) goto sigsplit; // Note: untaken branches don't consume BTB */
364 144 : reg[ dst ] = (ulong)((ulong)imm | ((ulong)fd_vm_instr_imm( text[ pc ] ) << 32));
365 144 : FD_VM_INTERP_INSTR_END;
366 :
367 36 : FD_VM_INTERP_INSTR_BEGIN(0x1c) /* FD_SBPF_OP_SUB_REG */
368 36 : reg[ dst ] = (ulong)(uint)( (int)reg_dst - (int)reg_src );
369 36 : FD_VM_INTERP_INSTR_END;
370 :
371 39 : FD_VM_INTERP_INSTR_BEGIN(0x1cdepr) /* FD_SBPF_OP_SUB_REG deprecated SIMD-0174 */
372 39 : reg[ dst ] = (ulong)(long)( (int)reg_dst - (int)reg_src );
373 39 : FD_VM_INTERP_INSTR_END;
374 :
375 648 : FD_VM_INTERP_BRANCH_BEGIN(0x1d) /* FD_SBPF_OP_JEQ_REG */
376 642 : pc += fd_ulong_if( reg_dst==reg_src, offset, 0UL );
377 642 : FD_VM_INTERP_BRANCH_END;
378 :
379 30093 : FD_VM_INTERP_INSTR_BEGIN(0x1f) /* FD_SBPF_OP_SUB64_REG */
380 30093 : reg[ dst ] = reg_dst - reg_src;
381 30093 : FD_VM_INTERP_INSTR_END;
382 :
383 : /* 0x20 - 0x2f ******************************************************/
384 :
385 42 : FD_VM_INTERP_INSTR_BEGIN(0x24) /* FD_SBPF_OP_MUL_IMM */
386 42 : reg[ dst ] = (ulong)(long)( (int)reg_dst * (int)imm );
387 42 : FD_VM_INTERP_INSTR_END;
388 :
389 3126 : FD_VM_INTERP_BRANCH_BEGIN(0x25) /* FD_SBPF_OP_JGT_IMM */
390 3096 : pc += fd_ulong_if( reg_dst>(ulong)(long)(int)imm, offset, 0UL );
391 3096 : FD_VM_INTERP_BRANCH_END;
392 :
393 9 : FD_VM_INTERP_INSTR_BEGIN(0x27) { /* FD_SBPF_OP_STB */
394 9 : ulong vaddr = reg_dst + offset;
395 9 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(uchar), region_haddr, region_st_sz, 1, 0UL );
396 9 : if( FD_UNLIKELY( !haddr ) ) {
397 6 : vm->segv_vaddr = vaddr;
398 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
399 6 : vm->segv_access_len = 1UL;
400 6 : goto sigsegv;
401 6 : } /* Note: untaken branches don't consume BTB */
402 3 : fd_vm_mem_st_1( haddr, (uchar)imm );
403 3 : }
404 3 : FD_VM_INTERP_INSTR_END;
405 :
406 78 : FD_VM_INTERP_INSTR_BEGIN(0x2c) { /* FD_SBPF_OP_LDXB */
407 78 : ulong vaddr = reg_src + offset;
408 78 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(uchar), region_haddr, region_ld_sz, 0, 0UL );
409 78 : if( FD_UNLIKELY( !haddr ) ) {
410 24 : vm->segv_vaddr = vaddr;
411 24 : vm->segv_access_type = FD_VM_ACCESS_TYPE_LD;
412 24 : vm->segv_access_len = 1UL;
413 24 : goto sigsegv;
414 24 : } /* Note: untaken branches don't consume BTB */
415 54 : reg[ dst ] = fd_vm_mem_ld_1( haddr );
416 54 : }
417 54 : FD_VM_INTERP_INSTR_END;
418 :
419 3117 : FD_VM_INTERP_BRANCH_BEGIN(0x2d) /* FD_SBPF_OP_JGT_REG */
420 3087 : pc += fd_ulong_if( reg_dst>reg_src, offset, 0UL );
421 3087 : FD_VM_INTERP_BRANCH_END;
422 :
423 1869 : FD_VM_INTERP_INSTR_BEGIN(0x2f) { /* FD_SBPF_OP_STXB */
424 1869 : ulong vaddr = reg_dst + offset;
425 1869 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(uchar), region_haddr, region_st_sz, 1, 0UL );
426 1869 : if( FD_UNLIKELY( !haddr ) ) {
427 30 : vm->segv_vaddr = vaddr;
428 30 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
429 30 : vm->segv_access_len = 1UL;
430 30 : goto sigsegv;
431 30 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigrdonly */
432 1839 : fd_vm_mem_st_1( haddr, (uchar)reg_src );
433 1839 : }
434 1839 : FD_VM_INTERP_INSTR_END;
435 :
436 42 : FD_VM_INTERP_INSTR_BEGIN(0x27depr) /* FD_SBPF_OP_MUL64_IMM */
437 42 : reg[ dst ] = (ulong)( (long)reg_dst * (long)(int)imm );
438 42 : FD_VM_INTERP_INSTR_END;
439 :
440 39 : FD_VM_INTERP_INSTR_BEGIN(0x2cdepr) /* FD_SBPF_OP_MUL_REG */
441 39 : reg[ dst ] = (ulong)(long)( (int)reg_dst * (int)reg_src );
442 39 : FD_VM_INTERP_INSTR_END;
443 :
444 30078 : FD_VM_INTERP_INSTR_BEGIN(0x2fdepr) /* FD_SBPF_OP_MUL64_REG */
445 30078 : reg[ dst ] = reg_dst * reg_src;
446 30078 : FD_VM_INTERP_INSTR_END;
447 :
448 : /* 0x30 - 0x3f ******************************************************/
449 :
450 42 : FD_VM_INTERP_INSTR_BEGIN(0x34) /* FD_SBPF_OP_DIV_IMM */
451 42 : /* FIXME: convert to a multiply at validation time (usually probably
452 42 : not worth it) */
453 42 : reg[ dst ] = (ulong)((uint)reg_dst / imm);
454 42 : FD_VM_INTERP_INSTR_END;
455 :
456 6123 : FD_VM_INTERP_BRANCH_BEGIN(0x35) /* FD_SBPF_OP_JGE_IMM */
457 6063 : pc += fd_ulong_if( reg_dst>=(ulong)(long)(int)imm, offset, 0UL );
458 6063 : FD_VM_INTERP_BRANCH_END;
459 :
460 3 : FD_VM_INTERP_INSTR_BEGIN(0x36) /* FD_SBPF_OP_UHMUL64_IMM */
461 3 : reg[ dst ] = (ulong)(( (uint128)reg_dst * (uint128)(ulong)imm ) >> 64 );
462 3 : FD_VM_INTERP_INSTR_END;
463 :
464 9 : FD_VM_INTERP_INSTR_BEGIN(0x37) { /* FD_SBPF_OP_STH */
465 9 : ulong vaddr = reg_dst + offset;
466 9 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(ushort), region_haddr, region_st_sz, 1, 0UL );
467 9 : int sigsegv = !haddr;
468 9 : if( FD_UNLIKELY( sigsegv ) ) {
469 6 : vm->segv_vaddr = vaddr;
470 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
471 6 : vm->segv_access_len = 2UL;
472 6 : goto sigsegv;
473 6 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
474 3 : fd_vm_mem_st_2( haddr, (ushort)imm );
475 3 : }
476 3 : FD_VM_INTERP_INSTR_END;
477 :
478 96 : FD_VM_INTERP_INSTR_BEGIN(0x3c) { /* FD_SBPF_OP_LDXH */
479 96 : ulong vaddr = reg_src + offset;
480 96 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(ushort), region_haddr, region_ld_sz, 0, 0UL );
481 96 : int sigsegv = !haddr;
482 96 : if( FD_UNLIKELY( sigsegv ) ) {
483 36 : vm->segv_vaddr = vaddr;
484 36 : vm->segv_access_type = FD_VM_ACCESS_TYPE_LD;
485 36 : vm->segv_access_len = 2UL;
486 36 : goto sigsegv; /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
487 36 : }
488 60 : reg[ dst ] = fd_vm_mem_ld_2( haddr );
489 60 : }
490 60 : FD_VM_INTERP_INSTR_END;
491 :
492 35532 : FD_VM_INTERP_BRANCH_BEGIN(0x3d) /* FD_SBPF_OP_JGE_REG */
493 35478 : pc += fd_ulong_if( reg_dst>=reg_src, offset, 0UL );
494 35478 : FD_VM_INTERP_BRANCH_END;
495 :
496 9 : FD_VM_INTERP_INSTR_BEGIN(0x3f) { /* FD_SBPF_OP_STXH */
497 9 : ulong vaddr = reg_dst + offset;
498 9 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(ushort), region_haddr, region_st_sz, 1, 0UL );
499 9 : int sigsegv = !haddr;
500 9 : if( FD_UNLIKELY( sigsegv ) ) {
501 6 : vm->segv_vaddr = vaddr;
502 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
503 6 : vm->segv_access_len = 2UL;
504 6 : goto sigsegv;
505 6 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
506 3 : fd_vm_mem_st_2( haddr, (ushort)reg_src );
507 3 : }
508 3 : FD_VM_INTERP_INSTR_END;
509 :
510 3 : FD_VM_INTERP_INSTR_BEGIN(0x3e) /* FD_SBPF_OP_UHMUL64_REG */
511 3 : reg[ dst ] = (ulong)(( (uint128)reg_dst * (uint128)reg_src ) >> 64 );
512 3 : FD_VM_INTERP_INSTR_END;
513 :
514 45 : FD_VM_INTERP_INSTR_BEGIN(0x37depr) /* FD_SBPF_OP_DIV64_IMM */
515 45 : reg[ dst ] = reg_dst / (ulong)(long)(int)imm;
516 45 : FD_VM_INTERP_INSTR_END;
517 :
518 57 : FD_VM_INTERP_INSTR_BEGIN(0x3cdepr) /* FD_SBPF_OP_DIV_REG */
519 57 : if( FD_UNLIKELY( !(uint)reg_src ) ) goto sigfpe;
520 42 : reg[ dst ] = (ulong)((uint)reg_dst / (uint)reg_src);
521 42 : FD_VM_INTERP_INSTR_END;
522 :
523 30072 : FD_VM_INTERP_INSTR_BEGIN(0x3fdepr) /* FD_SBPF_OP_DIV64_REG */
524 30072 : if( FD_UNLIKELY( !reg_src ) ) goto sigfpe;
525 30060 : reg[ dst ] = reg_dst / reg_src;
526 30060 : FD_VM_INTERP_INSTR_END;
527 :
528 : /* 0x40 - 0x4f ******************************************************/
529 :
530 51 : FD_VM_INTERP_INSTR_BEGIN(0x44) /* FD_SBPF_OP_OR_IMM */
531 51 : reg[ dst ] = (ulong)( (uint)reg_dst | imm );
532 51 : FD_VM_INTERP_INSTR_END;
533 :
534 1266 : FD_VM_INTERP_BRANCH_BEGIN(0x45) /* FD_SBPF_OP_JSET_IMM */
535 1254 : pc += fd_ulong_if( !!(reg_dst & (ulong)(long)(int)imm), offset, 0UL );
536 1254 : FD_VM_INTERP_BRANCH_END;
537 :
538 39 : FD_VM_INTERP_INSTR_BEGIN(0x46) /* FD_SBPF_OP_UDIV32_IMM */
539 39 : reg[ dst ] = (ulong)( (uint)reg_dst / (uint)imm );
540 39 : FD_VM_INTERP_INSTR_END;
541 :
542 51 : FD_VM_INTERP_INSTR_BEGIN(0x47) /* FD_SBPF_OP_OR64_IMM */
543 51 : reg[ dst ] = reg_dst | (ulong)(long)(int)imm;
544 51 : FD_VM_INTERP_INSTR_END;
545 :
546 57 : FD_VM_INTERP_INSTR_BEGIN(0x4c) /* FD_SBPF_OP_OR_REG */
547 57 : reg[ dst ] = (ulong)(uint)( reg_dst | reg_src );
548 57 : FD_VM_INTERP_INSTR_END;
549 :
550 663 : FD_VM_INTERP_BRANCH_BEGIN(0x4d) /* FD_SBPF_OP_JSET_REG */
551 657 : pc += fd_ulong_if( !!(reg_dst & reg_src), offset, 0UL );
552 657 : FD_VM_INTERP_BRANCH_END;
553 :
554 48 : FD_VM_INTERP_INSTR_BEGIN(0x4e) /* FD_SBPF_OP_UDIV32_REG */
555 48 : if( FD_UNLIKELY( !(uint)reg_src ) ) goto sigfpe;
556 36 : reg[ dst ] = (ulong)( (uint)reg_dst / (uint)reg_src );
557 36 : FD_VM_INTERP_INSTR_END;
558 :
559 57 : FD_VM_INTERP_INSTR_BEGIN(0x4f) /* FD_SBPF_OP_OR64_REG */
560 57 : reg[ dst ] = reg_dst | reg_src;
561 57 : FD_VM_INTERP_INSTR_END;
562 :
563 : /* 0x50 - 0x5f ******************************************************/
564 :
565 54 : FD_VM_INTERP_INSTR_BEGIN(0x54) /* FD_SBPF_OP_AND_IMM */
566 54 : reg[ dst ] = (ulong)( (uint)reg_dst & imm );
567 54 : FD_VM_INTERP_INSTR_END;
568 :
569 30669 : FD_VM_INTERP_BRANCH_BEGIN(0x55) /* FD_SBPF_OP_JNE_IMM */
570 30663 : pc += fd_ulong_if( reg_dst!=(ulong)(long)(int)imm, offset, 0UL );
571 30663 : FD_VM_INTERP_BRANCH_END;
572 :
573 39 : FD_VM_INTERP_INSTR_BEGIN(0x56) /* FD_SBPF_OP_UDIV64_IMM */
574 39 : reg[ dst ] = reg_dst / (ulong)imm;
575 39 : FD_VM_INTERP_INSTR_END;
576 :
577 63 : FD_VM_INTERP_INSTR_BEGIN(0x57) /* FD_SBPF_OP_AND64_IMM */
578 63 : reg[ dst ] = reg_dst & (ulong)(long)(int)imm;
579 63 : FD_VM_INTERP_INSTR_END;
580 :
581 60 : FD_VM_INTERP_INSTR_BEGIN(0x5c) /* FD_SBPF_OP_AND_REG */
582 60 : reg[ dst ] = (ulong)(uint)( reg_dst & reg_src );
583 60 : FD_VM_INTERP_INSTR_END;
584 :
585 657 : FD_VM_INTERP_BRANCH_BEGIN(0x5d) /* FD_SBPF_OP_JNE_REG */
586 651 : pc += fd_ulong_if( reg_dst!=reg_src, offset, 0UL );
587 651 : FD_VM_INTERP_BRANCH_END;
588 :
589 45 : FD_VM_INTERP_INSTR_BEGIN(0x5e) /* FD_SBPF_OP_UDIV64_REG */
590 45 : if( FD_UNLIKELY( !reg_src ) ) goto sigfpe;
591 36 : reg[ dst ] = reg_dst / reg_src;
592 36 : FD_VM_INTERP_INSTR_END;
593 :
594 48 : FD_VM_INTERP_INSTR_BEGIN(0x5f) /* FD_SBPF_OP_AND64_REG */
595 48 : reg[ dst ] = reg_dst & reg_src;
596 48 : FD_VM_INTERP_INSTR_END;
597 :
598 : /* 0x60 - 0x6f ******************************************************/
599 :
600 : /* FIXME: CHECK THE CU COST MODEL FOR THESE (IS IT LIKE
601 : FD_VM_CONSUME_MEM AND NOT JUST FIXED) */
602 : /* FIXME: MEM TRACING DIAGNOSTICS GO IN HERE */
603 :
604 453 : FD_VM_INTERP_INSTR_BEGIN(0x64) /* FD_SBPF_OP_LSH_IMM */
605 453 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L291 */
606 453 : reg[ dst ] = (ulong)( FD_RUST_UINT_WRAPPING_SHL( (uint)reg_dst, (uint)imm ) );
607 453 : FD_VM_INTERP_INSTR_END;
608 :
609 3702 : FD_VM_INTERP_BRANCH_BEGIN(0x65) /* FD_SBPF_OP_JSGT_IMM */
610 3666 : pc += fd_ulong_if( (long)reg_dst>(long)(int)imm, offset, 0UL );
611 3666 : FD_VM_INTERP_BRANCH_END;
612 :
613 39 : FD_VM_INTERP_INSTR_BEGIN(0x66) /* FD_SBPF_OP_UREM32_IMM */
614 39 : reg[ dst ] = (ulong)( (uint)reg_dst % (uint)imm );
615 39 : FD_VM_INTERP_INSTR_END;
616 :
617 456 : FD_VM_INTERP_INSTR_BEGIN(0x67) /* FD_SBPF_OP_LSH64_IMM */
618 456 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L376 */
619 456 : reg[ dst ] = FD_RUST_ULONG_WRAPPING_SHL( reg_dst, imm );
620 456 : FD_VM_INTERP_INSTR_END;
621 :
622 447 : FD_VM_INTERP_INSTR_BEGIN(0x6c) /* FD_SBPF_OP_LSH_REG */
623 447 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L292 */
624 447 : reg[ dst ] = (ulong)( FD_RUST_UINT_WRAPPING_SHL( (uint)reg_dst, reg_src ) );
625 447 : FD_VM_INTERP_INSTR_END;
626 :
627 3108 : FD_VM_INTERP_BRANCH_BEGIN(0x6d) /* FD_SBPF_OP_JSGT_REG */
628 3078 : pc += fd_ulong_if( (long)reg_dst>(long)reg_src, offset, 0UL );
629 3078 : FD_VM_INTERP_BRANCH_END;
630 :
631 48 : FD_VM_INTERP_INSTR_BEGIN(0x6e) /* FD_SBPF_OP_UREM32_REG */
632 48 : if( FD_UNLIKELY( !(uint)reg_src ) ) goto sigfpe;
633 36 : reg[ dst ] = (ulong)( (uint)reg_dst % (uint)reg_src );
634 36 : FD_VM_INTERP_INSTR_END;
635 :
636 9 : FD_VM_INTERP_INSTR_BEGIN(0x6f) /* FD_SBPF_OP_LSH64_REG */
637 9 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L377 */
638 9 : reg[ dst ] = FD_RUST_ULONG_WRAPPING_SHL( reg_dst, reg_src );
639 9 : FD_VM_INTERP_INSTR_END;
640 :
641 : /* 0x70 - 0x7f ******************************************************/
642 :
643 9 : FD_VM_INTERP_INSTR_BEGIN(0x74) /* FD_SBPF_OP_RSH_IMM */
644 9 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L293 */
645 9 : reg[ dst ] = (ulong)( FD_RUST_UINT_WRAPPING_SHR( (uint)reg_dst, imm ) );
646 9 : FD_VM_INTERP_INSTR_END;
647 :
648 6714 : FD_VM_INTERP_BRANCH_BEGIN(0x75) /* FD_SBPF_OP_JSGE_IMM */
649 6648 : pc += fd_ulong_if( (long)reg_dst>=(long)(int)imm, offset, 0UL );
650 6648 : FD_VM_INTERP_BRANCH_END;
651 :
652 39 : FD_VM_INTERP_INSTR_BEGIN(0x76) /* FD_SBPF_OP_UREM64_IMM */
653 39 : reg[ dst ] = reg_dst % (ulong)imm;
654 39 : FD_VM_INTERP_INSTR_END;
655 :
656 12 : FD_VM_INTERP_INSTR_BEGIN(0x77) /* FD_SBPF_OP_RSH64_IMM */
657 12 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L378 */
658 12 : reg[ dst ] = FD_RUST_ULONG_WRAPPING_SHR( reg_dst, imm );
659 12 : FD_VM_INTERP_INSTR_END;
660 :
661 9 : FD_VM_INTERP_INSTR_BEGIN(0x7c) /* FD_SBPF_OP_RSH_REG */
662 9 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L294 */
663 9 : reg[ dst ] = (ulong)( FD_RUST_UINT_WRAPPING_SHR( (uint)reg_dst, (uint)reg_src ) );
664 9 : FD_VM_INTERP_INSTR_END;
665 :
666 5508 : FD_VM_INTERP_BRANCH_BEGIN(0x7d) /* FD_SBPF_OP_JSGE_REG */
667 5454 : pc += fd_ulong_if( (long)reg_dst>=(long)reg_src, offset, 0UL );
668 5454 : FD_VM_INTERP_BRANCH_END;
669 :
670 45 : FD_VM_INTERP_INSTR_BEGIN(0x7e) /* FD_SBPF_OP_UREM64_REG */
671 45 : if( FD_UNLIKELY( !reg_src ) ) goto sigfpe;
672 36 : reg[ dst ] = reg_dst % reg_src;
673 36 : FD_VM_INTERP_INSTR_END;
674 :
675 9 : FD_VM_INTERP_INSTR_BEGIN(0x7f) /* FD_SBPF_OP_RSH64_REG */
676 9 : /* https://github.com/solana-labs/rbpf/blob/8d36530b7071060e2837ebb26f25590db6816048/src/interpreter.rs#L379 */
677 9 : reg[ dst ] = FD_RUST_ULONG_WRAPPING_SHR( reg_dst, reg_src );
678 9 : FD_VM_INTERP_INSTR_END;
679 :
680 : /* 0x80-0x8f ********************************************************/
681 :
682 3 : FD_VM_INTERP_INSTR_BEGIN(0x84) /* FD_SBPF_OP_NEG */
683 3 : reg[ dst ] = (ulong)( -(uint)reg_dst );
684 3 : FD_VM_INTERP_INSTR_END;
685 :
686 9 : FD_VM_INTERP_BRANCH_BEGIN(0x85) { /* FD_SBPF_OP_CALL_IMM */
687 :
688 9 : fd_sbpf_syscalls_t const * syscall = imm!=fd_sbpf_syscalls_key_null() ? fd_sbpf_syscalls_query_const( syscalls, (ulong)imm, NULL ) : NULL;
689 9 : if( FD_UNLIKELY( !syscall ) ) { /* Optimize for the syscall case */
690 :
691 : /* Note we do the stack push before updating the pc(*). This implies
692 : that the call stack frame gets allocated _before_ checking if the
693 : call target is valid. It would be fine to switch the order
694 : though such would change the precise faulting semantics of
695 : sigtextbr and sigstack.
696 :
697 : (*)but after checking calldests, see point below. */
698 :
699 : /* Agave's order of checks
700 : (https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L565-L572):
701 : 1. Lookup imm hash in FunctionRegistry (calldests_test is our equivalent)
702 : 2. Push stack frame
703 : 3. Check PC
704 : 4. Update PC
705 :
706 : Following this precisely is impossible as our PC check also
707 : serves as a bounds check for the calldests_test call. So we
708 : have to perform step 3 before step 1. The following
709 : is a best-effort implementation that should match the VM state
710 : in all ways except error code. */
711 :
712 : /* Special case to handle entrypoint.
713 : ebpf::hash_symbol_name(b"entrypoint") = 0xb00c380, and
714 : fd_pchash_inverse( 0xb00c380U ) = 0x71e3cf81U */
715 6 : if( FD_UNLIKELY( imm==0x71e3cf81U ) ) {
716 0 : FD_VM_INTERP_STACK_PUSH;
717 0 : pc = entry_pc - 1;
718 6 : } else {
719 6 : ulong target_pc = (ulong)fd_pchash_inverse( imm );
720 6 : if( FD_UNLIKELY( target_pc>=text_cnt ) ) {
721 6 : goto sigillbr; /* different return between 0x85 and 0x8d */
722 6 : }
723 0 : if( FD_UNLIKELY( !fd_sbpf_calldests_test( calldests, target_pc ) ) ) {
724 0 : goto sigillbr;
725 0 : }
726 0 : FD_VM_INTERP_STACK_PUSH;
727 0 : pc = target_pc - 1;
728 0 : }
729 :
730 6 : } else {
731 :
732 3 : FD_VM_INTERP_SYSCALL_EXEC;
733 :
734 3 : }
735 9 : } FD_VM_INTERP_BRANCH_END;
736 :
737 : /* SIMD-0178: Static syscalls (SBPF V3+)
738 : https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L542-L577 */
739 240 : FD_VM_INTERP_BRANCH_BEGIN(0x85_static) { /* FD_SBPF_OP_CALL_IMM (static syscalls) */
740 :
741 240 : if( src == 0 ) {
742 : /* External syscall
743 : https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L545-L553 */
744 15 : fd_sbpf_syscalls_t const * syscall = imm!=fd_sbpf_syscalls_key_null() ? fd_sbpf_syscalls_query_const( syscalls, (ulong)imm, NULL ) : NULL;
745 15 : if( FD_UNLIKELY( !syscall ) ) goto sigillbr;
746 18 : FD_VM_INTERP_SYSCALL_EXEC;
747 225 : } else if( src == 1 ) {
748 : /* Internal call
749 : https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L555-L563
750 : https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/program.rs#L97-L103 */
751 219 : long target_pc_l = fd_long_sat_add( (long)pc, fd_long_sat_add( (long)(int)imm, 1L ) );
752 219 : if( FD_UNLIKELY( target_pc_l<0L || (ulong)target_pc_l>=text_cnt ) ) goto sigillbr;
753 417 : FD_VM_INTERP_STACK_PUSH;
754 417 : pc = (ulong)target_pc_l - 1;
755 417 : } else {
756 : /* https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L574-L576 */
757 6 : goto sigillbr;
758 6 : }
759 :
760 240 : } FD_VM_INTERP_BRANCH_END;
761 :
762 39 : FD_VM_INTERP_INSTR_BEGIN(0x86) /* FD_SBPF_OP_LMUL32_IMM */
763 39 : reg[ dst ] = (ulong)( (uint)reg_dst * imm );
764 39 : FD_VM_INTERP_INSTR_END;
765 :
766 9 : FD_VM_INTERP_INSTR_BEGIN(0x87) { /* FD_SBPF_OP_STW */
767 9 : ulong vaddr = reg_dst + offset;
768 9 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(uint), region_haddr, region_st_sz, 1, 0UL );
769 9 : int sigsegv = !haddr;
770 9 : if( FD_UNLIKELY( sigsegv ) ) {
771 6 : vm->segv_vaddr = vaddr;
772 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
773 6 : vm->segv_access_len = 4UL;
774 6 : goto sigsegv;
775 6 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
776 3 : fd_vm_mem_st_4( haddr, imm );
777 3 : } FD_VM_INTERP_INSTR_END;
778 :
779 3 : FD_VM_INTERP_INSTR_BEGIN(0x87depr) /* FD_SBPF_OP_NEG64 deprecated */
780 3 : reg[ dst ] = -reg_dst;
781 3 : FD_VM_INTERP_INSTR_END;
782 :
783 108 : FD_VM_INTERP_INSTR_BEGIN(0x8c) { /* FD_SBPF_OP_LDXW */
784 108 : ulong vaddr = reg_src + offset;
785 108 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(uint), region_haddr, region_ld_sz, 0, 0UL );
786 108 : int sigsegv = !haddr;
787 108 : if( FD_UNLIKELY( sigsegv ) ) {
788 48 : vm->segv_vaddr = vaddr;
789 48 : vm->segv_access_type = FD_VM_ACCESS_TYPE_LD;
790 48 : vm->segv_access_len = 4UL;
791 48 : goto sigsegv; /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
792 48 : }
793 60 : reg[ dst ] = fd_vm_mem_ld_4( haddr );
794 60 : }
795 60 : FD_VM_INTERP_INSTR_END;
796 :
797 45 : FD_VM_INTERP_BRANCH_BEGIN(0x8d) { /* FD_SBPF_OP_CALL_REG */
798 :
799 45 : FD_VM_INTERP_STACK_PUSH;
800 :
801 : /* https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L528-L540 */
802 45 : ulong vaddr = fd_sbpf_callx_uses_src_reg_enabled( sbpf_version ) ? reg_src
803 45 : : fd_sbpf_callx_uses_dst_reg_enabled( sbpf_version ) ? reg[ dst ]
804 24 : : reg[ imm & 15U ];
805 :
806 : /* Notes: Agave checks region and target_pc before updating the pc.
807 : To match their state, we do the same, even though we could simply
808 : update the pc and let BRANCH_END fail.
809 : Also, Agave doesn't check alignment. */
810 :
811 45 : ulong region = vaddr >> 32;
812 : /* ulong align = vaddr & 7UL; */
813 45 : ulong target_pc = ((vaddr & FD_VM_OFFSET_MASK) - vm->text_off) / 8UL;
814 45 : if( FD_UNLIKELY( (region!=1UL) | (target_pc>=text_cnt) ) ) goto sigtextbr; /* Note: untaken branches don't consume BTB */
815 3 : pc = target_pc - 1;
816 :
817 3 : } FD_VM_INTERP_BRANCH_END;
818 :
819 33 : FD_VM_INTERP_INSTR_BEGIN(0x8e) /* FD_SBPF_OP_LMUL32_REG */
820 33 : reg[ dst ] = (ulong)( (uint)reg_dst * (uint)reg_src );
821 33 : FD_VM_INTERP_INSTR_END;
822 :
823 9 : FD_VM_INTERP_INSTR_BEGIN(0x8f) { /* FD_SBPF_OP_STXW */
824 9 : ulong vaddr = reg_dst + offset;
825 9 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(uint), region_haddr, region_st_sz, 1, 0UL );
826 9 : int sigsegv = !haddr;
827 9 : if( FD_UNLIKELY( sigsegv ) ) {
828 6 : vm->segv_vaddr = vaddr;
829 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
830 6 : vm->segv_access_len = 4UL;
831 6 : goto sigsegv;
832 6 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
833 3 : fd_vm_mem_st_4( haddr, (uint)reg_src );
834 3 : }
835 3 : FD_VM_INTERP_INSTR_END;
836 :
837 : /* 0x90 - 0x9f ******************************************************/
838 :
839 42 : FD_VM_INTERP_INSTR_BEGIN(0x94) /* FD_SBPF_OP_MOD_IMM */
840 42 : reg[ dst ] = (ulong)( (uint)reg_dst % imm );
841 42 : FD_VM_INTERP_INSTR_END;
842 :
843 8769 : FD_VM_INTERP_BRANCH_BEGIN(0x95) /* FD_SBPF_OP_EXIT */
844 8760 : /* Agave JIT VM exit implementation analysis below.
845 8760 :
846 8760 : Agave references:
847 8760 : https://github.com/solana-labs/rbpf/blob/v0.8.5/src/interpreter.rs#L503-L509
848 8760 : https://github.com/solana-labs/rbpf/blob/v0.8.5/src/jit.rs#L697-L702 */
849 8760 : if( FD_UNLIKELY( !frame_cnt ) ) goto sigexit; /* Exit program */
850 21 : frame_cnt--;
851 21 : reg[6] = shadow[ frame_cnt ].r6;
852 21 : reg[7] = shadow[ frame_cnt ].r7;
853 21 : reg[8] = shadow[ frame_cnt ].r8;
854 21 : reg[9] = shadow[ frame_cnt ].r9;
855 21 : reg[10] = shadow[ frame_cnt ].r10;
856 21 : pc = shadow[ frame_cnt ].pc;
857 21 : FD_VM_INTERP_BRANCH_END;
858 :
859 39 : FD_VM_INTERP_INSTR_BEGIN(0x96) /* FD_SBPF_OP_LMUL64_IMM */
860 39 : reg[ dst ] = reg_dst * (ulong)(long)(int)imm;
861 39 : FD_VM_INTERP_INSTR_END;
862 :
863 9 : FD_VM_INTERP_INSTR_BEGIN(0x97) { /* FD_SBPF_OP_STQ */
864 9 : ulong vaddr = reg_dst + offset;
865 9 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(ulong), region_haddr, region_st_sz, 1, 0UL );
866 9 : int sigsegv = !haddr;
867 9 : if( FD_UNLIKELY( sigsegv ) ) {
868 6 : vm->segv_vaddr = vaddr;
869 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
870 6 : vm->segv_access_len = 8UL;
871 6 : goto sigsegv;
872 6 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
873 3 : fd_vm_mem_st_8( haddr, (ulong)(long)(int)imm );
874 3 : }
875 3 : FD_VM_INTERP_INSTR_END;
876 :
877 84 : FD_VM_INTERP_INSTR_BEGIN(0x9c) { /* FD_SBPF_OP_LDXQ */
878 84 : ulong vaddr = reg_src + offset;
879 84 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(ulong), region_haddr, region_ld_sz, 0, 0UL );
880 84 : int sigsegv = !haddr;
881 84 : if( FD_UNLIKELY( sigsegv ) ) {
882 42 : vm->segv_vaddr = vaddr;
883 42 : vm->segv_access_type = FD_VM_ACCESS_TYPE_LD;
884 42 : vm->segv_access_len = 8UL;
885 42 : goto sigsegv; /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
886 42 : }
887 42 : reg[ dst ] = fd_vm_mem_ld_8( haddr );
888 42 : }
889 42 : FD_VM_INTERP_INSTR_END;
890 :
891 57 : FD_VM_INTERP_INSTR_BEGIN(0x9e) /* FD_SBPF_OP_LMUL64_REG */
892 57 : reg[ dst ] = reg_dst * reg_src;
893 57 : FD_VM_INTERP_INSTR_END;
894 :
895 780 : FD_VM_INTERP_INSTR_BEGIN(0x9f) { /* FD_SBPF_OP_STXQ */
896 780 : ulong vaddr = reg_dst + offset;
897 780 : ulong haddr = fd_vm_mem_haddr( vm, vaddr, sizeof(ulong), region_haddr, region_st_sz, 1, 0UL );
898 780 : int sigsegv = !haddr;
899 780 : if( FD_UNLIKELY( sigsegv ) ) {
900 6 : vm->segv_vaddr = vaddr;
901 6 : vm->segv_access_type = FD_VM_ACCESS_TYPE_ST;
902 6 : vm->segv_access_len = 8UL;
903 6 : goto sigsegv;
904 6 : } /* Note: untaken branches don't consume BTB */ /* FIXME: sigbus */
905 774 : fd_vm_mem_st_8( haddr, reg_src );
906 774 : }
907 774 : FD_VM_INTERP_INSTR_END;
908 :
909 42 : FD_VM_INTERP_INSTR_BEGIN(0x97depr) /* FD_SBPF_OP_MOD64_IMM */
910 42 : reg[ dst ] = reg_dst % (ulong)(long)(int)imm;
911 42 : FD_VM_INTERP_INSTR_END;
912 :
913 57 : FD_VM_INTERP_INSTR_BEGIN(0x9cdepr) /* FD_SBPF_OP_MOD_REG */
914 57 : if( FD_UNLIKELY( !(uint)reg_src ) ) goto sigfpe;
915 42 : reg[ dst ] = (ulong)( ((uint)reg_dst % (uint)reg_src) );
916 42 : FD_VM_INTERP_INSTR_END;
917 :
918 54 : FD_VM_INTERP_INSTR_BEGIN(0x9fdepr) /* FD_SBPF_OP_MOD64_REG */
919 54 : if( FD_UNLIKELY( !reg_src ) ) goto sigfpe;
920 42 : reg[ dst ] = reg_dst % reg_src;
921 42 : FD_VM_INTERP_INSTR_END;
922 :
923 : /* 0xa0 - 0xaf ******************************************************/
924 :
925 9 : FD_VM_INTERP_INSTR_BEGIN(0xa4) /* FD_SBPF_OP_XOR_IMM */
926 9 : reg[ dst ] = (ulong)( (uint)reg_dst ^ imm );
927 9 : FD_VM_INTERP_INSTR_END;
928 :
929 3126 : FD_VM_INTERP_BRANCH_BEGIN(0xa5) /* FD_SBPF_OP_JLT_IMM */
930 3096 : pc += fd_ulong_if( reg_dst<(ulong)(long)(int)imm, offset, 0UL );
931 3096 : FD_VM_INTERP_BRANCH_END;
932 :
933 9 : FD_VM_INTERP_INSTR_BEGIN(0xa7) /* FD_SBPF_OP_XOR64_IMM */
934 9 : reg[ dst ] = reg_dst ^ (ulong)(long)(int)imm;
935 9 : FD_VM_INTERP_INSTR_END;
936 :
937 9 : FD_VM_INTERP_INSTR_BEGIN(0xac) /* FD_SBPF_OP_XOR_REG */
938 9 : reg[ dst ] = (ulong)(uint)( reg_dst ^ reg_src );
939 9 : FD_VM_INTERP_INSTR_END;
940 :
941 2517 : FD_VM_INTERP_BRANCH_BEGIN(0xad) /* FD_SBPF_OP_JLT_REG */
942 2493 : pc += fd_ulong_if( reg_dst<reg_src, offset, 0UL );
943 2493 : FD_VM_INTERP_BRANCH_END;
944 :
945 21 : FD_VM_INTERP_INSTR_BEGIN(0xaf) /* FD_SBPF_OP_XOR64_REG */
946 21 : reg[ dst ] = reg_dst ^ reg_src;
947 21 : FD_VM_INTERP_INSTR_END;
948 :
949 : /* 0xb0 - 0xbf ******************************************************/
950 :
951 330 : FD_VM_INTERP_INSTR_BEGIN(0xb4) /* FD_SBPF_OP_MOV_IMM */
952 330 : reg[ dst ] = (ulong)imm;
953 330 : FD_VM_INTERP_INSTR_END;
954 :
955 6126 : FD_VM_INTERP_BRANCH_BEGIN(0xb5) /* FD_SBPF_OP_JLE_IMM */
956 6066 : pc += fd_ulong_if( reg_dst<=(ulong)(long)(int)imm, offset, 0UL );
957 6066 : FD_VM_INTERP_BRANCH_END;
958 :
959 3 : FD_VM_INTERP_INSTR_BEGIN(0xb6) /* FD_SBPF_OP_SHMUL64_IMM */
960 3 : reg[ dst ] = (ulong)(( (int128)(long)reg_dst * (int128)(long)(int)imm ) >> 64 );
961 3 : FD_VM_INTERP_INSTR_END;
962 :
963 64581 : FD_VM_INTERP_INSTR_BEGIN(0xb7) /* FD_SBPF_OP_MOV64_IMM */
964 64581 : reg[ dst ] = (ulong)(long)(int)imm;
965 64581 : FD_VM_INTERP_INSTR_END;
966 :
967 3 : FD_VM_INTERP_INSTR_BEGIN(0xbc) /* FD_SBPF_OP_MOV_REG */
968 3 : reg[ dst ] = (ulong)(long)(int)reg_src;
969 3 : FD_VM_INTERP_INSTR_END;
970 :
971 15 : FD_VM_INTERP_INSTR_BEGIN(0xbcdepr) /* FD_SBPF_OP_MOV_REG deprecated SIMD-1074 */
972 15 : reg[ dst ] = (ulong)(uint)reg_src;
973 15 : FD_VM_INTERP_INSTR_END;
974 :
975 4917 : FD_VM_INTERP_BRANCH_BEGIN(0xbd) /* FD_SBPF_OP_JLE_REG */
976 4869 : pc += fd_ulong_if( reg_dst<=reg_src, offset, 0UL );
977 4869 : FD_VM_INTERP_BRANCH_END;
978 :
979 3 : FD_VM_INTERP_INSTR_BEGIN(0xbe) /* FD_SBPF_OP_SHMUL64_REG */
980 3 : reg[ dst ] = (ulong)(( (int128)(long)reg_dst * (int128)(long)reg_src ) >> 64 );
981 3 : FD_VM_INTERP_INSTR_END;
982 :
983 60039 : FD_VM_INTERP_INSTR_BEGIN(0xbf) /* FD_SBPF_OP_MOV64_REG */
984 60039 : reg[ dst ] = reg_src;
985 60039 : FD_VM_INTERP_INSTR_END;
986 :
987 : /* 0xc0 - 0xcf ******************************************************/
988 :
989 147 : FD_VM_INTERP_INSTR_BEGIN(0xc4) /* FD_SBPF_OP_ARSH_IMM */
990 147 : reg[ dst ] = (ulong)(uint)( FD_RUST_INT_WRAPPING_SHR( (int)reg_dst, imm ) );
991 147 : FD_VM_INTERP_INSTR_END;
992 :
993 3102 : FD_VM_INTERP_BRANCH_BEGIN(0xc5) /* FD_SBPF_OP_JSLT_IMM */ /* FIXME: CHECK IMM SIGN EXTENSION */
994 3072 : pc += fd_ulong_if( (long)reg_dst<(long)(int)imm, offset, 0UL );
995 3072 : FD_VM_INTERP_BRANCH_END;
996 :
997 45 : FD_VM_INTERP_INSTR_BEGIN(0xc6) /* FD_SBPF_OP_SDIV32_IMM */
998 45 : if( FD_UNLIKELY( ((int)reg_dst==INT_MIN) & ((int)imm==-1) ) ) goto sigfpeof;
999 39 : reg[ dst ] = (ulong)(uint)( (int)reg_dst / (int)imm );
1000 39 : FD_VM_INTERP_INSTR_END;
1001 :
1002 135 : FD_VM_INTERP_INSTR_BEGIN(0xc7) /* FD_SBPF_OP_ARSH64_IMM */
1003 135 : reg[ dst ] = (ulong)( FD_RUST_LONG_WRAPPING_SHR( (long)reg_dst, imm ) );
1004 135 : FD_VM_INTERP_INSTR_END;
1005 :
1006 96 : FD_VM_INTERP_INSTR_BEGIN(0xcc) /* FD_SBPF_OP_ARSH_REG */
1007 96 : reg[ dst ] = (ulong)(uint)( FD_RUST_INT_WRAPPING_SHR( (int)reg_dst, (uint)reg_src ) );
1008 96 : FD_VM_INTERP_INSTR_END;
1009 :
1010 3108 : FD_VM_INTERP_BRANCH_BEGIN(0xcd) /* FD_SBPF_OP_JSLT_REG */
1011 3078 : pc += fd_ulong_if( (long)reg_dst<(long)reg_src, offset, 0UL );
1012 3078 : FD_VM_INTERP_BRANCH_END;
1013 :
1014 54 : FD_VM_INTERP_INSTR_BEGIN(0xce) /* FD_SBPF_OP_SDIV32_REG */
1015 54 : if( FD_UNLIKELY( !(int)reg_src ) ) goto sigfpe;
1016 42 : if( FD_UNLIKELY( ((int)reg_dst==INT_MIN) & ((int)reg_src==-1) ) ) goto sigfpeof;
1017 36 : reg[ dst ] = (ulong)(uint)( (int)reg_dst / (int)reg_src );
1018 36 : FD_VM_INTERP_INSTR_END;
1019 :
1020 93 : FD_VM_INTERP_INSTR_BEGIN(0xcf) /* FD_SBPF_OP_ARSH64_REG */
1021 93 : reg[ dst ] = (ulong)( FD_RUST_LONG_WRAPPING_SHR( (long)reg_dst, reg_src ) );
1022 93 : FD_VM_INTERP_INSTR_END;
1023 :
1024 : /* 0xd0 - 0xdf ******************************************************/
1025 :
1026 21 : FD_VM_INTERP_INSTR_BEGIN(0xd4) /* FD_SBPF_OP_END_LE */
1027 21 : switch( imm ) {
1028 9 : case 16U: reg[ dst ] = (ushort)reg_dst; break;
1029 3 : case 32U: reg[ dst ] = (uint) reg_dst; break;
1030 3 : case 64U: break;
1031 6 : default: goto siginv;
1032 21 : }
1033 15 : FD_VM_INTERP_INSTR_END;
1034 :
1035 2460 : FD_VM_INTERP_BRANCH_BEGIN(0xd5) /* FD_SBPF_OP_JSLE_IMM */
1036 2436 : pc += fd_ulong_if( (long)reg_dst<=(long)(int)imm, offset, 0UL );
1037 2436 : FD_VM_INTERP_BRANCH_END;
1038 :
1039 42 : FD_VM_INTERP_INSTR_BEGIN(0xd6) /* FD_SBPF_OP_SDIV64_IMM */
1040 42 : if( FD_UNLIKELY( ((long)reg_dst==LONG_MIN) & ((long)(int)imm==-1L) ) ) goto sigfpeof;
1041 39 : reg[ dst ] = (ulong)( (long)reg_dst / (long)(int)imm );
1042 39 : FD_VM_INTERP_INSTR_END;
1043 :
1044 75 : FD_VM_INTERP_INSTR_BEGIN(0xdc) /* FD_SBPF_OP_END_BE */
1045 75 : switch( imm ) {
1046 42 : case 16U: reg[ dst ] = (ulong)fd_ushort_bswap( (ushort)reg_dst ); break;
1047 12 : case 32U: reg[ dst ] = (ulong)fd_uint_bswap ( (uint) reg_dst ); break;
1048 9 : case 64U: reg[ dst ] = fd_ulong_bswap ( (ulong) reg_dst ); break;
1049 12 : default: goto siginv;
1050 75 : }
1051 63 : FD_VM_INTERP_INSTR_END;
1052 :
1053 1854 : FD_VM_INTERP_BRANCH_BEGIN(0xdd) /* FD_SBPF_OP_JSLE_REG */
1054 1836 : pc += fd_ulong_if( (long)reg_dst<=(long)reg_src, offset, 0UL );
1055 1836 : FD_VM_INTERP_BRANCH_END;
1056 :
1057 48 : FD_VM_INTERP_INSTR_BEGIN(0xde) /* FD_SBPF_OP_SDIV64_REG */
1058 48 : if( FD_UNLIKELY( !reg_src ) ) goto sigfpe;
1059 39 : if( FD_UNLIKELY( ((long)reg_dst==LONG_MIN) & ((long)reg_src==-1L) ) ) goto sigfpeof;
1060 36 : reg[ dst ] = (ulong)( (long)reg_dst / (long)reg_src );
1061 36 : FD_VM_INTERP_INSTR_END;
1062 :
1063 : /* 0xe0 - 0xef ******************************************************/
1064 :
1065 45 : FD_VM_INTERP_INSTR_BEGIN(0xe6) /* FD_SBPF_OP_SREM32_IMM */
1066 45 : if( FD_UNLIKELY( ((int)reg_dst==INT_MIN) & ((int)imm==-1) ) ) goto sigfpeof;
1067 39 : reg[ dst ] = (ulong)(uint)( (int)reg_dst % (int)imm );
1068 39 : FD_VM_INTERP_INSTR_END;
1069 :
1070 54 : FD_VM_INTERP_INSTR_BEGIN(0xee) /* FD_SBPF_OP_SREM32_REG */
1071 54 : if( FD_UNLIKELY( !(int)reg_src ) ) goto sigfpe;
1072 42 : if( FD_UNLIKELY( ((int)reg_dst==INT_MIN) & ((int)reg_src==-1) ) ) goto sigfpeof;
1073 36 : reg[ dst ] = (ulong)(uint)( (int)reg_dst % (int)reg_src );
1074 36 : FD_VM_INTERP_INSTR_END;
1075 :
1076 : /* 0xf0 - 0xff ******************************************************/
1077 :
1078 42 : FD_VM_INTERP_INSTR_BEGIN(0xf6) /* FD_SBPF_OP_SREM64_IMM */
1079 42 : if( FD_UNLIKELY( ((long)reg_dst==LONG_MIN) & ((long)(int)imm==-1L) ) ) goto sigfpeof;
1080 39 : reg[ dst ] = (ulong)( (long)reg_dst % (long)(int)imm );
1081 39 : FD_VM_INTERP_INSTR_END;
1082 :
1083 21 : FD_VM_INTERP_INSTR_BEGIN(0xf7) /* FD_SBPF_OP_HOR64 */
1084 21 : reg[ dst ] = reg_dst | (((ulong)imm) << 32);
1085 21 : FD_VM_INTERP_INSTR_END;
1086 :
1087 48 : FD_VM_INTERP_INSTR_BEGIN(0xfe) /* FD_SBPF_OP_SREM64_REG */
1088 48 : if( FD_UNLIKELY( !reg_src ) ) goto sigfpe;
1089 39 : if( FD_UNLIKELY( ((long)reg_dst==LONG_MIN) & ((long)reg_src==-1L) ) ) goto sigfpeof;
1090 36 : reg[ dst ] = (ulong)( (long)reg_dst % (long)reg_src );
1091 36 : FD_VM_INTERP_INSTR_END;
1092 :
1093 : /* SIMD-0377: JMP32
1094 : https://github.com/anza-xyz/sbpf/blob/v0.14.4/src/interpreter.rs#L480-L501
1095 :
1096 : 0x16 - 0xde ******************************************************/
1097 :
1098 1548 : FD_VM_INTERP_BRANCH_BEGIN(0x16_jmp32) /* FD_SBPF_OP_JEQ32_IMM */
1099 1533 : pc += fd_ulong_if( (uint)reg_dst==(uint)imm, offset, 0UL );
1100 1533 : FD_VM_INTERP_BRANCH_END;
1101 :
1102 630 : FD_VM_INTERP_BRANCH_BEGIN(0x1e_jmp32) /* FD_SBPF_OP_JEQ32_REG */
1103 624 : pc += fd_ulong_if( (uint)reg_dst==(uint)reg_src, offset, 0UL );
1104 624 : FD_VM_INTERP_BRANCH_END;
1105 :
1106 942 : FD_VM_INTERP_BRANCH_BEGIN(0x26_jmp32) /* FD_SBPF_OP_JGT32_IMM */
1107 933 : pc += fd_ulong_if( (uint)reg_dst>(uint)imm, offset, 0UL );
1108 933 : FD_VM_INTERP_BRANCH_END;
1109 :
1110 321 : FD_VM_INTERP_BRANCH_BEGIN(0x2e_jmp32) /* FD_SBPF_OP_JGT32_REG */
1111 318 : pc += fd_ulong_if( (uint)reg_dst>(uint)reg_src, offset, 0UL );
1112 318 : FD_VM_INTERP_BRANCH_END;
1113 :
1114 927 : FD_VM_INTERP_BRANCH_BEGIN(0x36_jmp32) /* FD_SBPF_OP_JGE32_IMM */
1115 918 : pc += fd_ulong_if( (uint)reg_dst>=(uint)imm, offset, 0UL );
1116 918 : FD_VM_INTERP_BRANCH_END;
1117 :
1118 318 : FD_VM_INTERP_BRANCH_BEGIN(0x3e_jmp32) /* FD_SBPF_OP_JGE32_REG */
1119 315 : pc += fd_ulong_if( (uint)reg_dst>=(uint)reg_src, offset, 0UL );
1120 315 : FD_VM_INTERP_BRANCH_END;
1121 :
1122 939 : FD_VM_INTERP_BRANCH_BEGIN(0x46_jmp32) /* FD_SBPF_OP_JSET32_IMM */
1123 930 : pc += fd_ulong_if( !!((uint)reg_dst & (uint)imm), offset, 0UL );
1124 930 : FD_VM_INTERP_BRANCH_END;
1125 :
1126 324 : FD_VM_INTERP_BRANCH_BEGIN(0x4e_jmp32) /* FD_SBPF_OP_JSET32_REG */
1127 321 : pc += fd_ulong_if( !!((uint)reg_dst & (uint)reg_src), offset, 0UL );
1128 321 : FD_VM_INTERP_BRANCH_END;
1129 :
1130 321 : FD_VM_INTERP_BRANCH_BEGIN(0x56_jmp32) /* FD_SBPF_OP_JNE32_IMM */
1131 318 : pc += fd_ulong_if( (uint)reg_dst!=(uint)imm, offset, 0UL );
1132 318 : FD_VM_INTERP_BRANCH_END;
1133 :
1134 324 : FD_VM_INTERP_BRANCH_BEGIN(0x5e_jmp32) /* FD_SBPF_OP_JNE32_REG */
1135 321 : pc += fd_ulong_if( (uint)reg_dst!=(uint)reg_src, offset, 0UL );
1136 321 : FD_VM_INTERP_BRANCH_END;
1137 :
1138 1248 : FD_VM_INTERP_BRANCH_BEGIN(0x66_jmp32) /* FD_SBPF_OP_JSGT32_IMM */
1139 1236 : pc += fd_ulong_if( (int)reg_dst>(int)imm, offset, 0UL );
1140 1236 : FD_VM_INTERP_BRANCH_END;
1141 :
1142 321 : FD_VM_INTERP_BRANCH_BEGIN(0x6e_jmp32) /* FD_SBPF_OP_JSGT32_REG */
1143 318 : pc += fd_ulong_if( (int)reg_dst>(int)reg_src, offset, 0UL );
1144 318 : FD_VM_INTERP_BRANCH_END;
1145 :
1146 627 : FD_VM_INTERP_BRANCH_BEGIN(0x76_jmp32) /* FD_SBPF_OP_JSGE32_IMM */
1147 621 : pc += fd_ulong_if( (int)reg_dst>=(int)imm, offset, 0UL );
1148 621 : FD_VM_INTERP_BRANCH_END;
1149 :
1150 318 : FD_VM_INTERP_BRANCH_BEGIN(0x7e_jmp32) /* FD_SBPF_OP_JSGE32_REG */
1151 315 : pc += fd_ulong_if( (int)reg_dst>=(int)reg_src, offset, 0UL );
1152 315 : FD_VM_INTERP_BRANCH_END;
1153 :
1154 627 : FD_VM_INTERP_BRANCH_BEGIN(0xa6_jmp32) /* FD_SBPF_OP_JLT32_IMM */
1155 621 : pc += fd_ulong_if( (uint)reg_dst<(uint)imm, offset, 0UL );
1156 621 : FD_VM_INTERP_BRANCH_END;
1157 :
1158 318 : FD_VM_INTERP_BRANCH_BEGIN(0xae_jmp32) /* FD_SBPF_OP_JLT32_REG */
1159 315 : pc += fd_ulong_if( (uint)reg_dst<(uint)reg_src, offset, 0UL );
1160 315 : FD_VM_INTERP_BRANCH_END;
1161 :
1162 621 : FD_VM_INTERP_BRANCH_BEGIN(0xb6_jmp32) /* FD_SBPF_OP_JLE32_IMM */
1163 615 : pc += fd_ulong_if( (uint)reg_dst<=(uint)imm, offset, 0UL );
1164 615 : FD_VM_INTERP_BRANCH_END;
1165 :
1166 318 : FD_VM_INTERP_BRANCH_BEGIN(0xbe_jmp32) /* FD_SBPF_OP_JLE32_REG */
1167 315 : pc += fd_ulong_if( (uint)reg_dst<=(uint)reg_src, offset, 0UL );
1168 315 : FD_VM_INTERP_BRANCH_END;
1169 :
1170 327 : FD_VM_INTERP_BRANCH_BEGIN(0xc6_jmp32) /* FD_SBPF_OP_JSLT32_IMM */
1171 324 : pc += fd_ulong_if( (int)reg_dst<(int)imm, offset, 0UL );
1172 324 : FD_VM_INTERP_BRANCH_END;
1173 :
1174 318 : FD_VM_INTERP_BRANCH_BEGIN(0xce_jmp32) /* FD_SBPF_OP_JSLT32_REG */
1175 315 : pc += fd_ulong_if( (int)reg_dst<(int)reg_src, offset, 0UL );
1176 315 : FD_VM_INTERP_BRANCH_END;
1177 :
1178 621 : FD_VM_INTERP_BRANCH_BEGIN(0xd6_jmp32) /* FD_SBPF_OP_JSLE32_IMM */
1179 615 : pc += fd_ulong_if( (int)reg_dst<=(int)imm, offset, 0UL );
1180 615 : FD_VM_INTERP_BRANCH_END;
1181 :
1182 318 : FD_VM_INTERP_BRANCH_BEGIN(0xde_jmp32) /* FD_SBPF_OP_JSLE32_REG */
1183 315 : pc += fd_ulong_if( (int)reg_dst<=(int)reg_src, offset, 0UL );
1184 315 : FD_VM_INTERP_BRANCH_END;
1185 :
1186 : /* FIXME: sigbus/sigrdonly are mapped to sigsegv for simplicity
1187 : currently but could be enabled if desired. */
1188 :
1189 : /* Note: sigtextbr is for sigtext errors that occur on branching
1190 : instructions (i.e., prefixed with FD_VM_INTERP_BRANCH_BEGIN).
1191 : We skip a repeat ic accumulation in FD_VM_INTERP_FAULT */
1192 :
1193 : /* FD_VM_INTERP_FAULT accumulates to ic and cu all non-faulting
1194 : instructions preceeding a fault generated by a non-branching
1195 : instruction. When a non-branching instruction faults, pc is at the
1196 : instruction and the number of non-branching instructions that have
1197 : not yet been reflected in ic and cu is:
1198 :
1199 : pc - pc0 + 1 - ic_correction
1200 :
1201 : as per the accounting described above. +1 to include the faulting
1202 : instruction itself.
1203 :
1204 : Note that, for a sigtext caused by a branch instruction, pc0==pc
1205 : (from the BRANCH_END) and ic_correction==0 (from the BRANCH_BEGIN)
1206 : such that the below does not change the already current values in
1207 : ic and cu. Thus it also "does the right thing" in both the
1208 : non-branching and branching cases for sigtext. The same applies to
1209 : sigsplit. */
1210 :
1211 0 : #define FD_VM_INTERP_FAULT \
1212 1659 : ic_correction = pc - pc0 + 1UL - ic_correction; \
1213 1659 : ic += ic_correction; \
1214 1659 : if ( FD_UNLIKELY( ic_correction > cu ) ) err = FD_VM_ERR_EBPF_EXCEEDED_MAX_INSTRUCTIONS; \
1215 1659 : cu -= fd_ulong_min( ic_correction, cu )
1216 :
1217 87 : sigtext: err = FD_VM_ERR_EBPF_EXECUTION_OVERRUN; FD_VM_INTERP_FAULT; goto interp_halt;
1218 42 : sigtextbr: err = FD_VM_ERR_EBPF_CALL_OUTSIDE_TEXT_SEGMENT; /* ic current */ /* cu current */ goto interp_halt;
1219 3 : sigstack: err = FD_VM_ERR_EBPF_CALL_DEPTH_EXCEEDED; /* ic current */ /* cu current */ goto interp_halt;
1220 1176 : sigill: err = FD_VM_ERR_EBPF_UNSUPPORTED_INSTRUCTION; FD_VM_INTERP_FAULT; goto interp_halt;
1221 27 : sigillbr: err = FD_VM_ERR_EBPF_UNSUPPORTED_INSTRUCTION; /* ic current */ /* cu current */ goto interp_halt;
1222 18 : siginv: err = FD_VM_ERR_EBPF_INVALID_INSTRUCTION; /* ic current */ /* cu current */ goto interp_halt;
1223 222 : sigsegv: err = fd_vm_generate_access_violation( vm->segv_vaddr, vm->sbpf_version ); FD_VM_INTERP_FAULT; goto interp_halt;
1224 807 : sigcost: err = FD_VM_ERR_EBPF_EXCEEDED_MAX_INSTRUCTIONS; /* ic current */ cu = 0UL; goto interp_halt;
1225 0 : sigsyscall: err = FD_VM_ERR_EBPF_SYSCALL_ERROR; /* ic current */ /* cu current */ goto interp_halt;
1226 138 : sigfpe: err = FD_VM_ERR_EBPF_DIVIDE_BY_ZERO; FD_VM_INTERP_FAULT; goto interp_halt;
1227 36 : sigfpeof: err = FD_VM_ERR_EBPF_DIVIDE_OVERFLOW; FD_VM_INTERP_FAULT; goto interp_halt;
1228 8739 : sigexit: /* err current */ /* ic current */ /* cu current */ goto interp_halt;
1229 :
1230 0 : #undef FD_VM_INTERP_FAULT
1231 :
1232 11295 : interp_halt:
1233 :
1234 : /* Pack the unpacked execution state into vm to give a precise view of
1235 : the execution when the vm halted. */
1236 :
1237 11295 : vm->pc = pc;
1238 11295 : vm->ic = ic;
1239 11295 : vm->cu = cu;
1240 11295 : vm->frame_cnt = frame_cnt;
1241 :
1242 11295 : # undef FD_VM_INTERP_STACK_PUSH
1243 :
1244 11295 : # undef FD_VM_INTERP_BRANCH_END
1245 11295 : # undef FD_VM_INTERP_BRANCH_BEGIN
1246 :
1247 11295 : # undef FD_VM_INTERP_INSTR_END
1248 11295 : # undef FD_VM_INTERP_INSTR_BEGIN
1249 11295 : # undef FD_VM_INTERP_INSTR_EXEC
1250 :
1251 11295 : # if defined(__clang__)
1252 11295 : # pragma clang diagnostic pop
1253 11295 : # endif
1254 :
1255 11295 : # if defined(__GNUC__)
1256 11295 : # pragma GCC diagnostic pop
1257 11295 : # endif
1258 :
1259 : /* Agave/JIT CU model analysis (and why we are conformant!):
1260 :
1261 : The Agave JIT employs a similar strategy of accumulating instructions
1262 : in a linear run and processing them at the start of a new linear
1263 : run/branch (side note: the JIT treats the LDQ instruction as a "branch"
1264 : that jumps pc + 2).
1265 :
1266 : In what is assumed to be an act of register conservation, the JIT
1267 : uses a catch-all "instruction meter" (IM) register (REGISTER_INSTRUCTION_METER)
1268 : that represents two different interpretations of the question
1269 : "how many instructions can I execute?".
1270 :
1271 : The IM, depending on where we are in the execution, either represents:
1272 : 1. IM => The number of instructions remaining before exhausting CU
1273 : budget. This is analagous to vm->cu in our interpreter.
1274 : 2. IM' => The last pc you can execute in the current linear run before
1275 : exhausting CU budget. Mathematically, IM' = IM + pc0
1276 : where pc0, just like our definition, is the start of the linear run.
1277 :
1278 : Note: IM' can go past the actual basic block/segment. In-fact,
1279 : it typically does, and implies we can execute the full block without
1280 : exhausting CU budget (reminder that LDQ is treated as a branch).
1281 :
1282 : By default, the IM' form is used during execution. The IM form is used:
1283 : - (transiently) during the processing of a branch instruction
1284 : - in post-VM cleanup (updates EbpfVm::previous_instruction_meter).
1285 :
1286 : When a branch instruction is encountered, the JIT checks
1287 : for CU exhaustion with pc > IM', and throws an exception if so. This is valid,
1288 : because as described above, IM' is the largest PC you can reach.
1289 :
1290 : If we haven't exhausted our CU limit, it updates IM':
1291 : 1. IM = IM' - (pc + 1) # Note that IM' at this point is IM + pc0',
1292 : # where pc0' is the start of the current linear run.
1293 : 2. IM' = IM + pc0 # pc0 is the start of the new linear run (typically the target pc)
1294 :
1295 : Code (that does the above in one ALU instruction):
1296 : https://github.com/solana-labs/rbpf/blob/v0.8.5/src/jit.rs#L891
1297 :
1298 :
1299 : ### How does this relate to our interpreter?
1300 :
1301 : This process is similar to FD_VM_INTERP_BRANCH_BEGIN.
1302 : We just deal with the IM form throughout (with vm->cu and ic_correction).
1303 : If we break down step 1 from above with what we know about IM and IM',
1304 : we get the following:
1305 : 1. IM = IM' - (pc + 1)
1306 : IM = (IM + pc0') - (pc + 1)
1307 : IM = IM + (pc0' - (pc + 1))
1308 : IM = IM - ((pc + 1) - pc0')
1309 : IM = IM - ic_correction
1310 : Here, ((pc + 1) - pc0') is the number of instrutions executed in the current
1311 : linear run. This is the same as our ic_correction(*) in FD_VM_INTERP_BRANCH_BEGIN.
1312 :
1313 : If we replace IM with cu, this effectively becomes the
1314 : cu -= ic_correction
1315 : line in FD_VM_INTERP_BRANCH_BEGIN.
1316 :
1317 : (*) Note: ic_correction (also) takes two forms. It is either the instruction
1318 : accumulator or the number of instructions executed in the current linear run.
1319 : It (transiently) takes the latter form during FD_VM_INTERP_BRANCH_BEGIN and
1320 : FD_VM_INTERP_FAULT, and the former form otherwise.
1321 : */
1322 :
1323 : /* (WIP) Precise faulting and the Agave JIT:
1324 :
1325 : Since the cost model is a part of consensus, we need to conform with the Agave/JIT
1326 : cost model 1:1. To achieve that, our faulting model also needs to match precisely. This
1327 : section covers the various faults that the respective VMs implement and how they match.
1328 :
1329 : # Normal VM exit (sigexit):
1330 : VM exit instruction entrypoint: https://github.com/solana-labs/rbpf/blob/12237895305ab38514be865ebed6268553e4f589/src/jit.rs#L698-L708
1331 :
1332 : Pseudocode (with FD semantics):
1333 : ```
1334 : # pc is at the exit instruction
1335 : # pc0 is the start of the current linear run
1336 : if (frame_cnt == 0) {
1337 : goto sigexit;
1338 : }
1339 : ...
1340 :
1341 : sigexit:
1342 : if IM' <= pc {
1343 : goto sigcost;
1344 : } else {
1345 : goto interp_halt;
1346 : }
1347 : ```
1348 :
1349 : Breaking down the IM' < pc check:
1350 : - IM' = IM + pc0
1351 : - pc = ic + pc0, where (ic + 1) is the number of instructions executed in the current linear run
1352 :
1353 : IM' <= pc
1354 : IM + pc0 <= ic + pc0
1355 : IM <= ic
1356 : IM <= pc - pc0
1357 : IM < pc - pc0 + 1 # all unsigned integers
1358 : IM < ic_correction
1359 :
1360 : This is analagous to the ic_correction>cu check in VM_INTERP_BRANCH_BEGIN.
1361 :
1362 : # (TODO) Text Overrun (sigtext/sigsplit):
1363 :
1364 : */
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