LCOV - code coverage report

Current view: top level - util/bits - fd_float.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 80 80 100.0 % Date: 2026-08-22 04:33:51 Functions: 57 338 16.9 %

Function Name	Hit count
fd_bundle_harness.c:fd_dblbits	0
fd_bundle_harness.c:fd_dblbits_bexp	0
fd_bundle_harness.c:fd_dblbits_bias	0
fd_bundle_harness.c:fd_dblbits_is_denorm	0
fd_bundle_harness.c:fd_dblbits_is_inf	0
fd_bundle_harness.c:fd_dblbits_is_nan	0
fd_bundle_harness.c:fd_dblbits_is_normal	0
fd_bundle_harness.c:fd_dblbits_is_zero	0
fd_bundle_harness.c:fd_dblbits_mant	0
fd_bundle_harness.c:fd_dblbits_pack	0
fd_bundle_harness.c:fd_dblbits_sign	0
fd_bundle_harness.c:fd_dblbits_unbias	0
fd_bundle_harness.c:fd_double	0
fd_bundle_harness.c:fd_float	0
fd_bundle_harness.c:fd_fltbits	0
fd_bundle_harness.c:fd_fltbits_bexp	0
fd_bundle_harness.c:fd_fltbits_bias	0
fd_bundle_harness.c:fd_fltbits_is_denorm	0
fd_bundle_harness.c:fd_fltbits_is_inf	0
fd_bundle_harness.c:fd_fltbits_is_nan	0
fd_bundle_harness.c:fd_fltbits_is_normal	0
fd_bundle_harness.c:fd_fltbits_is_zero	0
fd_bundle_harness.c:fd_fltbits_mant	0
fd_bundle_harness.c:fd_fltbits_pack	0
fd_bundle_harness.c:fd_fltbits_sign	0
fd_bundle_harness.c:fd_fltbits_unbias	0
fd_genesis_create.c:fd_dblbits	0
fd_genesis_create.c:fd_dblbits_bexp	0
fd_genesis_create.c:fd_dblbits_bias	0
fd_genesis_create.c:fd_dblbits_is_denorm	0
fd_genesis_create.c:fd_dblbits_is_inf	0
fd_genesis_create.c:fd_dblbits_is_nan	0
fd_genesis_create.c:fd_dblbits_is_normal	0
fd_genesis_create.c:fd_dblbits_is_zero	0
fd_genesis_create.c:fd_dblbits_mant	0
fd_genesis_create.c:fd_dblbits_pack	0
fd_genesis_create.c:fd_dblbits_sign	0
fd_genesis_create.c:fd_dblbits_unbias	0
fd_genesis_create.c:fd_double	0
fd_genesis_create.c:fd_float	0
fd_genesis_create.c:fd_fltbits	0
fd_genesis_create.c:fd_fltbits_bexp	0
fd_genesis_create.c:fd_fltbits_bias	0
fd_genesis_create.c:fd_fltbits_is_denorm	0
fd_genesis_create.c:fd_fltbits_is_inf	0
fd_genesis_create.c:fd_fltbits_is_nan	0
fd_genesis_create.c:fd_fltbits_is_normal	0
fd_genesis_create.c:fd_fltbits_is_zero	0
fd_genesis_create.c:fd_fltbits_mant	0
fd_genesis_create.c:fd_fltbits_pack	0
fd_genesis_create.c:fd_fltbits_sign	0
fd_genesis_create.c:fd_fltbits_unbias	0
fd_rewards.c:fd_dblbits	0
fd_rewards.c:fd_dblbits_bexp	0
fd_rewards.c:fd_dblbits_bias	0
fd_rewards.c:fd_dblbits_is_denorm	0
fd_rewards.c:fd_dblbits_is_inf	0
fd_rewards.c:fd_dblbits_is_nan	0
fd_rewards.c:fd_dblbits_is_normal	0
fd_rewards.c:fd_dblbits_is_zero	0
fd_rewards.c:fd_dblbits_mant	0
fd_rewards.c:fd_dblbits_pack	0
fd_rewards.c:fd_dblbits_sign	0
fd_rewards.c:fd_dblbits_unbias	0
fd_rewards.c:fd_double	0
fd_rewards.c:fd_float	0
fd_rewards.c:fd_fltbits	0
fd_rewards.c:fd_fltbits_bexp	0
fd_rewards.c:fd_fltbits_bias	0
fd_rewards.c:fd_fltbits_is_denorm	0
fd_rewards.c:fd_fltbits_is_inf	0
fd_rewards.c:fd_fltbits_is_nan	0
fd_rewards.c:fd_fltbits_is_normal	0
fd_rewards.c:fd_fltbits_is_zero	0
fd_rewards.c:fd_fltbits_mant	0
fd_rewards.c:fd_fltbits_pack	0
fd_rewards.c:fd_fltbits_sign	0
fd_rewards.c:fd_fltbits_unbias	0
fd_runtime.c:fd_dblbits	0
fd_runtime.c:fd_dblbits_bexp	0
fd_runtime.c:fd_dblbits_bias	0
fd_runtime.c:fd_dblbits_is_denorm	0
fd_runtime.c:fd_dblbits_is_inf	0
fd_runtime.c:fd_dblbits_is_nan	0
fd_runtime.c:fd_dblbits_is_normal	0
fd_runtime.c:fd_dblbits_is_zero	0
fd_runtime.c:fd_dblbits_mant	0
fd_runtime.c:fd_dblbits_pack	0
fd_runtime.c:fd_dblbits_sign	0
fd_runtime.c:fd_dblbits_unbias	0
fd_runtime.c:fd_double	0
fd_runtime.c:fd_float	0
fd_runtime.c:fd_fltbits	0
fd_runtime.c:fd_fltbits_bexp	0
fd_runtime.c:fd_fltbits_bias	0
fd_runtime.c:fd_fltbits_is_denorm	0
fd_runtime.c:fd_fltbits_is_inf	0
fd_runtime.c:fd_fltbits_is_nan	0
fd_runtime.c:fd_fltbits_is_normal	0
fd_runtime.c:fd_fltbits_is_zero	0
fd_runtime.c:fd_fltbits_mant	0
fd_runtime.c:fd_fltbits_pack	0
fd_runtime.c:fd_fltbits_sign	0
fd_runtime.c:fd_fltbits_unbias	0
fd_stake_delegations.c:fd_dblbits	0
fd_stake_delegations.c:fd_dblbits_bexp	0
fd_stake_delegations.c:fd_dblbits_bias	0
fd_stake_delegations.c:fd_dblbits_is_denorm	0
fd_stake_delegations.c:fd_dblbits_is_inf	0
fd_stake_delegations.c:fd_dblbits_is_nan	0
fd_stake_delegations.c:fd_dblbits_is_normal	0
fd_stake_delegations.c:fd_dblbits_is_zero	0
fd_stake_delegations.c:fd_dblbits_mant	0
fd_stake_delegations.c:fd_dblbits_pack	0
fd_stake_delegations.c:fd_dblbits_sign	0
fd_stake_delegations.c:fd_dblbits_unbias	0
fd_stake_delegations.c:fd_double	0
fd_stake_delegations.c:fd_float	0
fd_stake_delegations.c:fd_fltbits	0
fd_stake_delegations.c:fd_fltbits_bexp	0
fd_stake_delegations.c:fd_fltbits_bias	0
fd_stake_delegations.c:fd_fltbits_is_denorm	0
fd_stake_delegations.c:fd_fltbits_is_inf	0
fd_stake_delegations.c:fd_fltbits_is_nan	0
fd_stake_delegations.c:fd_fltbits_is_normal	0
fd_stake_delegations.c:fd_fltbits_is_zero	0
fd_stake_delegations.c:fd_fltbits_mant	0
fd_stake_delegations.c:fd_fltbits_pack	0
fd_stake_delegations.c:fd_fltbits_sign	0
fd_stake_delegations.c:fd_fltbits_unbias	0
fd_stakes.c:fd_dblbits	0
fd_stakes.c:fd_dblbits_bexp	0
fd_stakes.c:fd_dblbits_bias	0
fd_stakes.c:fd_dblbits_is_denorm	0
fd_stakes.c:fd_dblbits_is_inf	0
fd_stakes.c:fd_dblbits_is_nan	0
fd_stakes.c:fd_dblbits_is_normal	0
fd_stakes.c:fd_dblbits_is_zero	0
fd_stakes.c:fd_dblbits_mant	0
fd_stakes.c:fd_dblbits_pack	0
fd_stakes.c:fd_dblbits_sign	0
fd_stakes.c:fd_dblbits_unbias	0
fd_stakes.c:fd_double	0
fd_stakes.c:fd_float	0
fd_stakes.c:fd_fltbits	0
fd_stakes.c:fd_fltbits_bexp	0
fd_stakes.c:fd_fltbits_bias	0
fd_stakes.c:fd_fltbits_is_denorm	0
fd_stakes.c:fd_fltbits_is_inf	0
fd_stakes.c:fd_fltbits_is_nan	0
fd_stakes.c:fd_fltbits_is_normal	0
fd_stakes.c:fd_fltbits_is_zero	0
fd_stakes.c:fd_fltbits_mant	0
fd_stakes.c:fd_fltbits_pack	0
fd_stakes.c:fd_fltbits_sign	0
fd_stakes.c:fd_fltbits_unbias	0
fd_sysvar_rent1.c:fd_dblbits_bias	0
fd_sysvar_rent1.c:fd_dblbits_is_denorm	0
fd_sysvar_rent1.c:fd_dblbits_is_inf	0
fd_sysvar_rent1.c:fd_dblbits_is_nan	0
fd_sysvar_rent1.c:fd_dblbits_is_normal	0
fd_sysvar_rent1.c:fd_dblbits_is_zero	0
fd_sysvar_rent1.c:fd_dblbits_pack	0
fd_sysvar_rent1.c:fd_dblbits_unbias	0
fd_sysvar_rent1.c:fd_double	0
fd_sysvar_rent1.c:fd_float	0
fd_sysvar_rent1.c:fd_fltbits	0
fd_sysvar_rent1.c:fd_fltbits_bexp	0
fd_sysvar_rent1.c:fd_fltbits_bias	0
fd_sysvar_rent1.c:fd_fltbits_is_denorm	0
fd_sysvar_rent1.c:fd_fltbits_is_inf	0
fd_sysvar_rent1.c:fd_fltbits_is_nan	0
fd_sysvar_rent1.c:fd_fltbits_is_normal	0
fd_sysvar_rent1.c:fd_fltbits_is_zero	0
fd_sysvar_rent1.c:fd_fltbits_mant	0
fd_sysvar_rent1.c:fd_fltbits_pack	0
fd_sysvar_rent1.c:fd_fltbits_sign	0
fd_sysvar_rent1.c:fd_fltbits_unbias	0
test_bundle_exec.c:fd_dblbits	0
test_bundle_exec.c:fd_dblbits_bexp	0
test_bundle_exec.c:fd_dblbits_bias	0
test_bundle_exec.c:fd_dblbits_is_denorm	0
test_bundle_exec.c:fd_dblbits_is_inf	0
test_bundle_exec.c:fd_dblbits_is_nan	0
test_bundle_exec.c:fd_dblbits_is_normal	0
test_bundle_exec.c:fd_dblbits_is_zero	0
test_bundle_exec.c:fd_dblbits_mant	0
test_bundle_exec.c:fd_dblbits_pack	0
test_bundle_exec.c:fd_dblbits_sign	0
test_bundle_exec.c:fd_dblbits_unbias	0
test_bundle_exec.c:fd_double	0
test_bundle_exec.c:fd_float	0
test_bundle_exec.c:fd_fltbits	0
test_bundle_exec.c:fd_fltbits_bexp	0
test_bundle_exec.c:fd_fltbits_bias	0
test_bundle_exec.c:fd_fltbits_is_denorm	0
test_bundle_exec.c:fd_fltbits_is_inf	0
test_bundle_exec.c:fd_fltbits_is_nan	0
test_bundle_exec.c:fd_fltbits_is_normal	0
test_bundle_exec.c:fd_fltbits_is_zero	0
test_bundle_exec.c:fd_fltbits_mant	0
test_bundle_exec.c:fd_fltbits_pack	0
test_bundle_exec.c:fd_fltbits_sign	0
test_bundle_exec.c:fd_fltbits_unbias	0
test_cast.c:fd_dblbits_bias	0
test_cast.c:fd_dblbits_is_denorm	0
test_cast.c:fd_dblbits_is_inf	0
test_cast.c:fd_dblbits_is_nan	0
test_cast.c:fd_dblbits_is_normal	0
test_cast.c:fd_dblbits_is_zero	0
test_cast.c:fd_dblbits_unbias	0
test_cast.c:fd_float	0
test_cast.c:fd_fltbits	0
test_cast.c:fd_fltbits_bexp	0
test_cast.c:fd_fltbits_bias	0
test_cast.c:fd_fltbits_is_denorm	0
test_cast.c:fd_fltbits_is_inf	0
test_cast.c:fd_fltbits_is_nan	0
test_cast.c:fd_fltbits_is_normal	0
test_cast.c:fd_fltbits_is_zero	0
test_cast.c:fd_fltbits_mant	0
test_cast.c:fd_fltbits_pack	0
test_cast.c:fd_fltbits_sign	0
test_cast.c:fd_fltbits_unbias	0
test_float.c:fd_dblbits_is_normal	0
test_float.c:fd_fltbits_is_normal	0
test_inflation_rate.c:fd_dblbits	0
test_inflation_rate.c:fd_dblbits_bexp	0
test_inflation_rate.c:fd_dblbits_bias	0
test_inflation_rate.c:fd_dblbits_is_denorm	0
test_inflation_rate.c:fd_dblbits_is_inf	0
test_inflation_rate.c:fd_dblbits_is_nan	0
test_inflation_rate.c:fd_dblbits_is_normal	0
test_inflation_rate.c:fd_dblbits_is_zero	0
test_inflation_rate.c:fd_dblbits_mant	0
test_inflation_rate.c:fd_dblbits_pack	0
test_inflation_rate.c:fd_dblbits_sign	0
test_inflation_rate.c:fd_dblbits_unbias	0
test_inflation_rate.c:fd_double	0
test_inflation_rate.c:fd_float	0
test_inflation_rate.c:fd_fltbits	0
test_inflation_rate.c:fd_fltbits_bexp	0
test_inflation_rate.c:fd_fltbits_bias	0
test_inflation_rate.c:fd_fltbits_is_denorm	0
test_inflation_rate.c:fd_fltbits_is_inf	0
test_inflation_rate.c:fd_fltbits_is_nan	0
test_inflation_rate.c:fd_fltbits_is_normal	0
test_inflation_rate.c:fd_fltbits_is_zero	0
test_inflation_rate.c:fd_fltbits_mant	0
test_inflation_rate.c:fd_fltbits_pack	0
test_inflation_rate.c:fd_fltbits_sign	0
test_inflation_rate.c:fd_fltbits_unbias	0
test_rust_float.c:fd_dblbits_bias	0
test_rust_float.c:fd_dblbits_unbias	0
test_rust_float.c:fd_float	0
test_rust_float.c:fd_fltbits_bias	0
test_rust_float.c:fd_fltbits_pack	0
test_rust_float.c:fd_fltbits_sign	0
test_rust_float.c:fd_fltbits_unbias	0
test_warmup_cooldown_allowance.c:fd_dblbits_bias	0
test_warmup_cooldown_allowance.c:fd_dblbits_is_denorm	0
test_warmup_cooldown_allowance.c:fd_dblbits_is_inf	0
test_warmup_cooldown_allowance.c:fd_dblbits_is_nan	0
test_warmup_cooldown_allowance.c:fd_dblbits_is_normal	0
test_warmup_cooldown_allowance.c:fd_dblbits_is_zero	0
test_warmup_cooldown_allowance.c:fd_dblbits_pack	0
test_warmup_cooldown_allowance.c:fd_dblbits_unbias	0
test_warmup_cooldown_allowance.c:fd_double	0
test_warmup_cooldown_allowance.c:fd_float	0
test_warmup_cooldown_allowance.c:fd_fltbits	0
test_warmup_cooldown_allowance.c:fd_fltbits_bexp	0
test_warmup_cooldown_allowance.c:fd_fltbits_bias	0
test_warmup_cooldown_allowance.c:fd_fltbits_is_denorm	0
test_warmup_cooldown_allowance.c:fd_fltbits_is_inf	0
test_warmup_cooldown_allowance.c:fd_fltbits_is_nan	0
test_warmup_cooldown_allowance.c:fd_fltbits_is_normal	0
test_warmup_cooldown_allowance.c:fd_fltbits_is_zero	0
test_warmup_cooldown_allowance.c:fd_fltbits_mant	0
test_warmup_cooldown_allowance.c:fd_fltbits_pack	0
test_warmup_cooldown_allowance.c:fd_fltbits_sign	0
test_warmup_cooldown_allowance.c:fd_fltbits_unbias	0
test_cast.c:fd_dblbits_pack	9
test_cast.c:fd_double	9
test_cast.c:fd_dblbits_mant	12
test_cast.c:fd_dblbits_sign	18
test_cast.c:fd_dblbits	21
test_float.c:fd_dblbits	30
test_float.c:fd_dblbits_bias	30
test_float.c:fd_dblbits_sign	30
test_float.c:fd_dblbits_unbias	30
test_float.c:fd_double	30
test_float.c:fd_float	30
test_float.c:fd_fltbits	30
test_float.c:fd_fltbits_bias	30
test_float.c:fd_fltbits_sign	30
test_float.c:fd_fltbits_unbias	30
test_cast.c:fd_dblbits_bexp	33
fd_sysvar_rent1.c:fd_dblbits_mant	54
fd_sysvar_rent1.c:fd_dblbits_sign	57
fd_sysvar_rent1.c:fd_dblbits_bexp	114
test_rust_float.c:fd_dblbits_is_normal	489
test_rust_float.c:fd_dblbits_pack	489
test_rust_float.c:fd_fltbits_is_normal	489
test_rust_float.c:fd_dblbits_is_denorm	978
test_rust_float.c:fd_dblbits_is_inf	978
test_rust_float.c:fd_fltbits	978
test_rust_float.c:fd_fltbits_is_denorm	978
test_rust_float.c:fd_fltbits_is_inf	978
test_rust_float.c:fd_fltbits_is_nan	978
test_rust_float.c:fd_fltbits_is_zero	978
test_rust_float.c:fd_dblbits_sign	1449
test_rust_float.c:fd_dblbits_is_nan	1467
test_rust_float.c:fd_dblbits_is_zero	1473
test_rust_float.c:fd_double	3459
test_rust_float.c:fd_fltbits_bexp	3912
test_rust_float.c:fd_fltbits_mant	3912
test_rust_float.c:fd_dblbits_mant	6054
test_rust_float.c:fd_dblbits_bexp	6645
test_rust_float.c:fd_dblbits	17115
fd_sysvar_rent1.c:fd_dblbits	54192
test_float.c:fd_dblbits_is_denorm	98304
test_float.c:fd_fltbits_is_denorm	98304
test_float.c:fd_dblbits_is_nan	98310
test_float.c:fd_fltbits_is_nan	98310
test_warmup_cooldown_allowance.c:fd_dblbits_mant	5684376
test_warmup_cooldown_allowance.c:fd_dblbits	6000003
test_warmup_cooldown_allowance.c:fd_dblbits_sign	6000003
test_warmup_cooldown_allowance.c:fd_dblbits_bexp	12000006
test_float.c:fd_dblbits_is_inf	12582918
test_float.c:fd_dblbits_is_zero	12582918
test_float.c:fd_fltbits_is_inf	12582918
test_float.c:fd_fltbits_is_zero	12582918
test_float.c:fd_dblbits_bexp	25362480
test_float.c:fd_dblbits_mant	25362480
test_float.c:fd_dblbits_pack	25362480
test_float.c:fd_fltbits_bexp	25362480
test_float.c:fd_fltbits_mant	25362480
test_float.c:fd_fltbits_pack	25362480

Generated by: LCOV version 1.14