LCOV - code coverage report

Current view: top level - util/simd - fd_avx512_wwl.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 85 85 100.0 % Date: 2024-11-14 11:55:10 Functions: 9 312 2.9 %

Function Name	Hit count
fd_address_lookup_table_program.c:wwl_ld	0
fd_address_lookup_table_program.c:wwl_ldu	0
fd_address_lookup_table_program.c:wwl_rol_variable	0
fd_address_lookup_table_program.c:wwl_rol_vector	0
fd_address_lookup_table_program.c:wwl_ror_variable	0
fd_address_lookup_table_program.c:wwl_ror_vector	0
fd_address_lookup_table_program.c:wwl_st	0
fd_address_lookup_table_program.c:wwl_stu	0
fd_curve25519.c:wwl_ld	0
fd_curve25519.c:wwl_ldu	0
fd_curve25519.c:wwl_rol_variable	0
fd_curve25519.c:wwl_rol_vector	0
fd_curve25519.c:wwl_ror_variable	0
fd_curve25519.c:wwl_ror_vector	0
fd_curve25519.c:wwl_st	0
fd_curve25519.c:wwl_stu	0
fd_ed25519_user.c:wwl_ld	0
fd_ed25519_user.c:wwl_ldu	0
fd_ed25519_user.c:wwl_rol_variable	0
fd_ed25519_user.c:wwl_rol_vector	0
fd_ed25519_user.c:wwl_ror_variable	0
fd_ed25519_user.c:wwl_ror_vector	0
fd_ed25519_user.c:wwl_st	0
fd_ed25519_user.c:wwl_stu	0
fd_f25519.c:wwl_ld	0
fd_f25519.c:wwl_ldu	0
fd_f25519.c:wwl_rol_variable	0
fd_f25519.c:wwl_rol_vector	0
fd_f25519.c:wwl_ror_variable	0
fd_f25519.c:wwl_ror_vector	0
fd_f25519.c:wwl_st	0
fd_f25519.c:wwl_stu	0
fd_pack.c:wwl_ld	0
fd_pack.c:wwl_ldu	0
fd_pack.c:wwl_rol_variable	0
fd_pack.c:wwl_rol_vector	0
fd_pack.c:wwl_ror_variable	0
fd_pack.c:wwl_ror_vector	0
fd_pack.c:wwl_st	0
fd_pack.c:wwl_stu	0
fd_pubkey_utils.c:wwl_ld	0
fd_pubkey_utils.c:wwl_ldu	0
fd_pubkey_utils.c:wwl_rol_variable	0
fd_pubkey_utils.c:wwl_rol_vector	0
fd_pubkey_utils.c:wwl_ror_variable	0
fd_pubkey_utils.c:wwl_ror_vector	0
fd_pubkey_utils.c:wwl_st	0
fd_pubkey_utils.c:wwl_stu	0
fd_r43x6.c:wwl_ld	0
fd_r43x6.c:wwl_ldu	0
fd_r43x6.c:wwl_rol_variable	0
fd_r43x6.c:wwl_rol_vector	0
fd_r43x6.c:wwl_ror_variable	0
fd_r43x6.c:wwl_ror_vector	0
fd_r43x6.c:wwl_st	0
fd_r43x6.c:wwl_stu	0
fd_r43x6_ge.c:wwl_ld	0
fd_r43x6_ge.c:wwl_ldu	0
fd_r43x6_ge.c:wwl_rol_variable	0
fd_r43x6_ge.c:wwl_rol_vector	0
fd_r43x6_ge.c:wwl_ror_variable	0
fd_r43x6_ge.c:wwl_ror_vector	0
fd_r43x6_ge.c:wwl_st	0
fd_r43x6_ge.c:wwl_stu	0
fd_rangeproofs.c:wwl_ld	0
fd_rangeproofs.c:wwl_ldu	0
fd_rangeproofs.c:wwl_rol_variable	0
fd_rangeproofs.c:wwl_rol_vector	0
fd_rangeproofs.c:wwl_ror_variable	0
fd_rangeproofs.c:wwl_ror_vector	0
fd_rangeproofs.c:wwl_st	0
fd_rangeproofs.c:wwl_stu	0
fd_ristretto255.c:wwl_ld	0
fd_ristretto255.c:wwl_ldu	0
fd_ristretto255.c:wwl_rol_variable	0
fd_ristretto255.c:wwl_rol_vector	0
fd_ristretto255.c:wwl_ror_variable	0
fd_ristretto255.c:wwl_ror_vector	0
fd_ristretto255.c:wwl_st	0
fd_ristretto255.c:wwl_stu	0
fd_sha256_batch_avx512.c:wwl_ld	0
fd_sha256_batch_avx512.c:wwl_ldu	0
fd_sha256_batch_avx512.c:wwl_rol_variable	0
fd_sha256_batch_avx512.c:wwl_rol_vector	0
fd_sha256_batch_avx512.c:wwl_ror_variable	0
fd_sha256_batch_avx512.c:wwl_ror_vector	0
fd_sha256_batch_avx512.c:wwl_st	0
fd_sha256_batch_avx512.c:wwl_stu	0
fd_sha512_batch_avx512.c:wwl_ld	0
fd_sha512_batch_avx512.c:wwl_ldu	0
fd_sha512_batch_avx512.c:wwl_rol_variable	0
fd_sha512_batch_avx512.c:wwl_rol_vector	0
fd_sha512_batch_avx512.c:wwl_ror_variable	0
fd_sha512_batch_avx512.c:wwl_ror_vector	0
fd_sha512_batch_avx512.c:wwl_st	0
fd_sha512_batch_avx512.c:wwl_stu	0
fd_vm_syscall_cpi.c:wwl_ld	0
fd_vm_syscall_cpi.c:wwl_ldu	0
fd_vm_syscall_cpi.c:wwl_rol_variable	0
fd_vm_syscall_cpi.c:wwl_rol_vector	0
fd_vm_syscall_cpi.c:wwl_ror_variable	0
fd_vm_syscall_cpi.c:wwl_ror_vector	0
fd_vm_syscall_cpi.c:wwl_st	0
fd_vm_syscall_cpi.c:wwl_stu	0
fd_vm_syscall_curve.c:wwl_ld	0
fd_vm_syscall_curve.c:wwl_ldu	0
fd_vm_syscall_curve.c:wwl_rol_variable	0
fd_vm_syscall_curve.c:wwl_rol_vector	0
fd_vm_syscall_curve.c:wwl_ror_variable	0
fd_vm_syscall_curve.c:wwl_ror_vector	0
fd_vm_syscall_curve.c:wwl_st	0
fd_vm_syscall_curve.c:wwl_stu	0
fd_vm_syscall_pda.c:wwl_ld	0
fd_vm_syscall_pda.c:wwl_ldu	0
fd_vm_syscall_pda.c:wwl_rol_variable	0
fd_vm_syscall_pda.c:wwl_rol_vector	0
fd_vm_syscall_pda.c:wwl_ror_variable	0
fd_vm_syscall_pda.c:wwl_ror_vector	0
fd_vm_syscall_pda.c:wwl_st	0
fd_vm_syscall_pda.c:wwl_stu	0
fd_wsample.c:wwl_ld	0
fd_wsample.c:wwl_ldu	0
fd_wsample.c:wwl_rol_variable	0
fd_wsample.c:wwl_rol_vector	0
fd_wsample.c:wwl_ror_variable	0
fd_wsample.c:wwl_ror_vector	0
fd_wsample.c:wwl_st	0
fd_wsample.c:wwl_stu	0
fd_x25519.c:wwl_ld	0
fd_x25519.c:wwl_ldu	0
fd_x25519.c:wwl_rol_variable	0
fd_x25519.c:wwl_rol_vector	0
fd_x25519.c:wwl_ror_variable	0
fd_x25519.c:wwl_ror_vector	0
fd_x25519.c:wwl_st	0
fd_x25519.c:wwl_stu	0
fd_zksdk.c:wwl_ld	0
fd_zksdk.c:wwl_ldu	0
fd_zksdk.c:wwl_rol_variable	0
fd_zksdk.c:wwl_rol_vector	0
fd_zksdk.c:wwl_ror_variable	0
fd_zksdk.c:wwl_ror_vector	0
fd_zksdk.c:wwl_st	0
fd_zksdk.c:wwl_stu	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_ld	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_ldu	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_rol_variable	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_rol_vector	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_ror_variable	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_ror_vector	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_st	0
fd_zksdk_batched_grouped_ciphertext_2_handles_validity.c:wwl_stu	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_ld	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_ldu	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_rol_variable	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_rol_vector	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_ror_variable	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_ror_vector	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_st	0
fd_zksdk_batched_grouped_ciphertext_3_handles_validity.c:wwl_stu	0
fd_zksdk_batched_range_proof_u128.c:wwl_ld	0
fd_zksdk_batched_range_proof_u128.c:wwl_ldu	0
fd_zksdk_batched_range_proof_u128.c:wwl_rol_variable	0
fd_zksdk_batched_range_proof_u128.c:wwl_rol_vector	0
fd_zksdk_batched_range_proof_u128.c:wwl_ror_variable	0
fd_zksdk_batched_range_proof_u128.c:wwl_ror_vector	0
fd_zksdk_batched_range_proof_u128.c:wwl_st	0
fd_zksdk_batched_range_proof_u128.c:wwl_stu	0
fd_zksdk_batched_range_proof_u256.c:wwl_ld	0
fd_zksdk_batched_range_proof_u256.c:wwl_ldu	0
fd_zksdk_batched_range_proof_u256.c:wwl_rol_variable	0
fd_zksdk_batched_range_proof_u256.c:wwl_rol_vector	0
fd_zksdk_batched_range_proof_u256.c:wwl_ror_variable	0
fd_zksdk_batched_range_proof_u256.c:wwl_ror_vector	0
fd_zksdk_batched_range_proof_u256.c:wwl_st	0
fd_zksdk_batched_range_proof_u256.c:wwl_stu	0
fd_zksdk_batched_range_proof_u64.c:wwl_ld	0
fd_zksdk_batched_range_proof_u64.c:wwl_ldu	0
fd_zksdk_batched_range_proof_u64.c:wwl_rol_variable	0
fd_zksdk_batched_range_proof_u64.c:wwl_rol_vector	0
fd_zksdk_batched_range_proof_u64.c:wwl_ror_variable	0
fd_zksdk_batched_range_proof_u64.c:wwl_ror_vector	0
fd_zksdk_batched_range_proof_u64.c:wwl_st	0
fd_zksdk_batched_range_proof_u64.c:wwl_stu	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_ld	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_ldu	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_rol_variable	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_rol_vector	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_ror_variable	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_ror_vector	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_st	0
fd_zksdk_ciphertext_ciphertext_equality.c:wwl_stu	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_ld	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_ldu	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_rol_variable	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_rol_vector	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_ror_variable	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_ror_vector	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_st	0
fd_zksdk_ciphertext_commitment_equality.c:wwl_stu	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_ld	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_ldu	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_rol_variable	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_rol_vector	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_ror_variable	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_ror_vector	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_st	0
fd_zksdk_grouped_ciphertext_2_handles_validity.c:wwl_stu	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_ld	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_ldu	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_rol_variable	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_rol_vector	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_ror_variable	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_ror_vector	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_st	0
fd_zksdk_grouped_ciphertext_3_handles_validity.c:wwl_stu	0
fd_zksdk_percentage_with_cap.c:wwl_ld	0
fd_zksdk_percentage_with_cap.c:wwl_ldu	0
fd_zksdk_percentage_with_cap.c:wwl_rol_variable	0
fd_zksdk_percentage_with_cap.c:wwl_rol_vector	0
fd_zksdk_percentage_with_cap.c:wwl_ror_variable	0
fd_zksdk_percentage_with_cap.c:wwl_ror_vector	0
fd_zksdk_percentage_with_cap.c:wwl_st	0
fd_zksdk_percentage_with_cap.c:wwl_stu	0
fd_zksdk_pubkey_validity.c:wwl_ld	0
fd_zksdk_pubkey_validity.c:wwl_ldu	0
fd_zksdk_pubkey_validity.c:wwl_rol_variable	0
fd_zksdk_pubkey_validity.c:wwl_rol_vector	0
fd_zksdk_pubkey_validity.c:wwl_ror_variable	0
fd_zksdk_pubkey_validity.c:wwl_ror_vector	0
fd_zksdk_pubkey_validity.c:wwl_st	0
fd_zksdk_pubkey_validity.c:wwl_stu	0
fd_zksdk_zero_ciphertext.c:wwl_ld	0
fd_zksdk_zero_ciphertext.c:wwl_ldu	0
fd_zksdk_zero_ciphertext.c:wwl_rol_variable	0
fd_zksdk_zero_ciphertext.c:wwl_rol_vector	0
fd_zksdk_zero_ciphertext.c:wwl_ror_variable	0
fd_zksdk_zero_ciphertext.c:wwl_ror_vector	0
fd_zksdk_zero_ciphertext.c:wwl_st	0
fd_zksdk_zero_ciphertext.c:wwl_stu	0
test_avx512_16x32.c:wwl_ld	0
test_avx512_16x32.c:wwl_ldu	0
test_avx512_16x32.c:wwl_rol_variable	0
test_avx512_16x32.c:wwl_rol_vector	0
test_avx512_16x32.c:wwl_ror_variable	0
test_avx512_16x32.c:wwl_ror_vector	0
test_avx512_16x32.c:wwl_stu	0
test_chkdup.c:wwl_ld	0
test_chkdup.c:wwl_ldu	0
test_chkdup.c:wwl_rol_variable	0
test_chkdup.c:wwl_rol_vector	0
test_chkdup.c:wwl_ror_variable	0
test_chkdup.c:wwl_ror_vector	0
test_chkdup.c:wwl_st	0
test_chkdup.c:wwl_stu	0
test_ed25519.c:wwl_ld	0
test_ed25519.c:wwl_ldu	0
test_ed25519.c:wwl_rol_variable	0
test_ed25519.c:wwl_rol_vector	0
test_ed25519.c:wwl_ror_variable	0
test_ed25519.c:wwl_ror_vector	0
test_ed25519.c:wwl_st	0
test_ed25519.c:wwl_stu	0
test_map_perfect.c:wwl_ld	0
test_map_perfect.c:wwl_ldu	0
test_map_perfect.c:wwl_rol_variable	0
test_map_perfect.c:wwl_rol_vector	0
test_map_perfect.c:wwl_ror_variable	0
test_map_perfect.c:wwl_ror_vector	0
test_map_perfect.c:wwl_st	0
test_map_perfect.c:wwl_stu	0
test_pack_bitset.c:wwl_ld	0
test_pack_bitset.c:wwl_ldu	0
test_pack_bitset.c:wwl_rol_variable	0
test_pack_bitset.c:wwl_rol_vector	0
test_pack_bitset.c:wwl_ror_variable	0
test_pack_bitset.c:wwl_ror_vector	0
test_pack_bitset.c:wwl_st	0
test_pack_bitset.c:wwl_stu	0
test_r43x6.c:wwl_ld	0
test_r43x6.c:wwl_ldu	0
test_r43x6.c:wwl_rol_variable	0
test_r43x6.c:wwl_rol_vector	0
test_r43x6.c:wwl_ror_variable	0
test_r43x6.c:wwl_ror_vector	0
test_r43x6.c:wwl_st	0
test_r43x6.c:wwl_stu	0
test_ristretto255.c:wwl_ld	0
test_ristretto255.c:wwl_ldu	0
test_ristretto255.c:wwl_rol_variable	0
test_ristretto255.c:wwl_rol_vector	0
test_ristretto255.c:wwl_ror_variable	0
test_ristretto255.c:wwl_ror_vector	0
test_ristretto255.c:wwl_st	0
test_ristretto255.c:wwl_stu	0
test_zksdk.c:wwl_ld	0
test_zksdk.c:wwl_ldu	0
test_zksdk.c:wwl_rol_variable	0
test_zksdk.c:wwl_rol_vector	0
test_zksdk.c:wwl_ror_variable	0
test_zksdk.c:wwl_ror_vector	0
test_zksdk.c:wwl_st	0
test_zksdk.c:wwl_stu	0
test_avx512_8x64.c:wwl_ld	1000000
test_avx512_8x64.c:wwl_ldu	1000000
test_avx512_8x64.c:wwl_rol_variable	1000000
test_avx512_8x64.c:wwl_rol_vector	1000000
test_avx512_8x64.c:wwl_ror_variable	1000000
test_avx512_8x64.c:wwl_ror_vector	1000000
test_avx512_8x64.c:wwl_stu	1000000
test_avx512_16x32.c:wwl_st	4000000
test_avx512_8x64.c:wwl_st	205000000

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