LCOV - code coverage report

Current view: top level - util/simd - fd_sse_vl.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 82 94 87.2 % Date: 2024-11-14 11:55:10 Functions: 23 182 12.6 %

Function Name	Hit count
fd_aes_gcm_x86.c:_vl_gather	0
fd_aes_gcm_x86.c:vl_abs	0
fd_aes_gcm_x86.c:vl_extract_variable	0
fd_aes_gcm_x86.c:vl_insert_variable	0
fd_aes_gcm_x86.c:vl_ld	0
fd_aes_gcm_x86.c:vl_ldu	0
fd_aes_gcm_x86.c:vl_max	0
fd_aes_gcm_x86.c:vl_max_all	0
fd_aes_gcm_x86.c:vl_min	0
fd_aes_gcm_x86.c:vl_min_all	0
fd_aes_gcm_x86.c:vl_rol	0
fd_aes_gcm_x86.c:vl_rol_variable	0
fd_aes_gcm_x86.c:vl_rol_vector	0
fd_aes_gcm_x86.c:vl_ror	0
fd_aes_gcm_x86.c:vl_ror_variable	0
fd_aes_gcm_x86.c:vl_ror_vector	0
fd_aes_gcm_x86.c:vl_shr	0
fd_aes_gcm_x86.c:vl_shr_variable	0
fd_aes_gcm_x86.c:vl_shr_vector	0
fd_aes_gcm_x86.c:vl_st	0
fd_aes_gcm_x86.c:vl_stu	0
fd_aes_gcm_x86.c:vl_sum_all	0
fd_aes_gcm_x86.c:vl_to_vd	0
fd_aes_gcm_x86.c:vl_to_vf	0
fd_aes_gcm_x86.c:vl_to_vi	0
fd_aes_gcm_x86.c:vl_to_vu	0
fd_chacha20_sse.c:_vl_gather	0
fd_chacha20_sse.c:vl_abs	0
fd_chacha20_sse.c:vl_extract_variable	0
fd_chacha20_sse.c:vl_insert_variable	0
fd_chacha20_sse.c:vl_ld	0
fd_chacha20_sse.c:vl_ldu	0
fd_chacha20_sse.c:vl_max	0
fd_chacha20_sse.c:vl_max_all	0
fd_chacha20_sse.c:vl_min	0
fd_chacha20_sse.c:vl_min_all	0
fd_chacha20_sse.c:vl_rol	0
fd_chacha20_sse.c:vl_rol_variable	0
fd_chacha20_sse.c:vl_rol_vector	0
fd_chacha20_sse.c:vl_ror	0
fd_chacha20_sse.c:vl_ror_variable	0
fd_chacha20_sse.c:vl_ror_vector	0
fd_chacha20_sse.c:vl_shr	0
fd_chacha20_sse.c:vl_shr_variable	0
fd_chacha20_sse.c:vl_shr_vector	0
fd_chacha20_sse.c:vl_st	0
fd_chacha20_sse.c:vl_stu	0
fd_chacha20_sse.c:vl_sum_all	0
fd_chacha20_sse.c:vl_to_vd	0
fd_chacha20_sse.c:vl_to_vf	0
fd_chacha20_sse.c:vl_to_vi	0
fd_chacha20_sse.c:vl_to_vu	0
fd_reedsol_pi.c:_vl_gather	0
fd_reedsol_pi.c:vl_abs	0
fd_reedsol_pi.c:vl_extract_variable	0
fd_reedsol_pi.c:vl_insert_variable	0
fd_reedsol_pi.c:vl_ld	0
fd_reedsol_pi.c:vl_ldu	0
fd_reedsol_pi.c:vl_max	0
fd_reedsol_pi.c:vl_max_all	0
fd_reedsol_pi.c:vl_min	0
fd_reedsol_pi.c:vl_min_all	0
fd_reedsol_pi.c:vl_rol	0
fd_reedsol_pi.c:vl_rol_variable	0
fd_reedsol_pi.c:vl_rol_vector	0
fd_reedsol_pi.c:vl_ror	0
fd_reedsol_pi.c:vl_ror_variable	0
fd_reedsol_pi.c:vl_ror_vector	0
fd_reedsol_pi.c:vl_shr	0
fd_reedsol_pi.c:vl_shr_variable	0
fd_reedsol_pi.c:vl_shr_vector	0
fd_reedsol_pi.c:vl_st	0
fd_reedsol_pi.c:vl_stu	0
fd_reedsol_pi.c:vl_sum_all	0
fd_reedsol_pi.c:vl_to_vd	0
fd_reedsol_pi.c:vl_to_vf	0
fd_reedsol_pi.c:vl_to_vi	0
fd_reedsol_pi.c:vl_to_vu	0
test_sse_16x8.c:_vl_gather	0
test_sse_16x8.c:vl_abs	0
test_sse_16x8.c:vl_extract_variable	0
test_sse_16x8.c:vl_insert_variable	0
test_sse_16x8.c:vl_ld	0
test_sse_16x8.c:vl_ldu	0
test_sse_16x8.c:vl_max	0
test_sse_16x8.c:vl_max_all	0
test_sse_16x8.c:vl_min	0
test_sse_16x8.c:vl_min_all	0
test_sse_16x8.c:vl_rol	0
test_sse_16x8.c:vl_rol_variable	0
test_sse_16x8.c:vl_rol_vector	0
test_sse_16x8.c:vl_ror	0
test_sse_16x8.c:vl_ror_variable	0
test_sse_16x8.c:vl_ror_vector	0
test_sse_16x8.c:vl_shr	0
test_sse_16x8.c:vl_shr_variable	0
test_sse_16x8.c:vl_shr_vector	0
test_sse_16x8.c:vl_st	0
test_sse_16x8.c:vl_stu	0
test_sse_16x8.c:vl_sum_all	0
test_sse_16x8.c:vl_to_vd	0
test_sse_16x8.c:vl_to_vf	0
test_sse_16x8.c:vl_to_vi	0
test_sse_16x8.c:vl_to_vu	0
test_sse_2x64.c:_vl_gather	0
test_sse_2x64.c:vl_extract_variable	0
test_sse_2x64.c:vl_insert_variable	0
test_sse_2x64.c:vl_ld	0
test_sse_2x64.c:vl_ldu	0
test_sse_2x64.c:vl_rol_vector	0
test_sse_2x64.c:vl_ror_vector	0
test_sse_2x64.c:vl_shr_vector	0
test_sse_2x64.c:vl_st	0
test_sse_2x64.c:vl_stu	0
test_sse_4x32.c:_vl_gather	0
test_sse_4x32.c:vl_abs	0
test_sse_4x32.c:vl_extract_variable	0
test_sse_4x32.c:vl_insert_variable	0
test_sse_4x32.c:vl_ld	0
test_sse_4x32.c:vl_ldu	0
test_sse_4x32.c:vl_max	0
test_sse_4x32.c:vl_max_all	0
test_sse_4x32.c:vl_min	0
test_sse_4x32.c:vl_min_all	0
test_sse_4x32.c:vl_rol	0
test_sse_4x32.c:vl_rol_variable	0
test_sse_4x32.c:vl_rol_vector	0
test_sse_4x32.c:vl_ror	0
test_sse_4x32.c:vl_ror_variable	0
test_sse_4x32.c:vl_ror_vector	0
test_sse_4x32.c:vl_shr	0
test_sse_4x32.c:vl_shr_variable	0
test_sse_4x32.c:vl_shr_vector	0
test_sse_4x32.c:vl_st	0
test_sse_4x32.c:vl_stu	0
test_sse_4x32.c:vl_sum_all	0
test_sse_4x32.c:vl_to_vd	0
test_sse_4x32.c:vl_to_vf	0
test_sse_4x32.c:vl_to_vi	0
test_sse_4x32.c:vl_to_vu	0
test_sse_common.c:vl_abs	0
test_sse_common.c:vl_max	0
test_sse_common.c:vl_max_all	0
test_sse_common.c:vl_min	0
test_sse_common.c:vl_min_all	0
test_sse_common.c:vl_rol	0
test_sse_common.c:vl_rol_variable	0
test_sse_common.c:vl_rol_vector	0
test_sse_common.c:vl_ror	0
test_sse_common.c:vl_ror_variable	0
test_sse_common.c:vl_ror_vector	0
test_sse_common.c:vl_shr	0
test_sse_common.c:vl_shr_variable	0
test_sse_common.c:vl_shr_vector	0
test_sse_common.c:vl_sum_all	0
test_sse_common.c:vl_to_vd	0
test_sse_common.c:vl_to_vf	0
test_sse_common.c:vl_to_vi	0
test_sse_common.c:vl_to_vu	0
test_sse_2x64.c:vl_abs	131072
test_sse_2x64.c:vl_max_all	196608
test_sse_2x64.c:vl_min_all	196608
test_sse_2x64.c:vl_sum_all	196608
test_sse_2x64.c:vl_to_vd	196608
test_sse_2x64.c:vl_max	262144
test_sse_2x64.c:vl_min	262144
test_sse_2x64.c:vl_to_vf	393216
test_sse_2x64.c:vl_to_vi	393216
test_sse_2x64.c:vl_to_vu	393216
test_sse_2x64.c:vl_rol	8388608
test_sse_2x64.c:vl_ror	8388608
test_sse_2x64.c:vl_rol_variable	12582912
test_sse_2x64.c:vl_ror_variable	12582912
test_sse_2x64.c:vl_shr	12582912
test_sse_2x64.c:vl_shr_variable	12582912
test_sse_common.c:vl_ld	141361203
test_sse_common.c:vl_st	141361203
test_sse_common.c:vl_extract_variable	282722406
test_sse_common.c:vl_insert_variable	282722406
test_sse_common.c:vl_ldu	282722406
test_sse_common.c:vl_stu	282722406
test_sse_common.c:_vl_gather	565444812

Generated by: LCOV version 1.14