LCOV - code coverage report

Current view: top level - util/simd - fd_sse_vu.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 88 96 91.7 % Date: 2025-08-07 04:53:16 Functions: 25 178 14.0 %

Function Name	Hit count
fd_aes_gcm_x86.c:vu_bcast_pair	0
fd_aes_gcm_x86.c:vu_bcast_wide	0
fd_aes_gcm_x86.c:vu_extract_variable	0
fd_aes_gcm_x86.c:vu_gather	0
fd_aes_gcm_x86.c:vu_insert_variable	0
fd_aes_gcm_x86.c:vu_ld	0
fd_aes_gcm_x86.c:vu_ldu	0
fd_aes_gcm_x86.c:vu_max_all	0
fd_aes_gcm_x86.c:vu_min_all	0
fd_aes_gcm_x86.c:vu_rol	0
fd_aes_gcm_x86.c:vu_rol_variable	0
fd_aes_gcm_x86.c:vu_rol_vector	0
fd_aes_gcm_x86.c:vu_ror	0
fd_aes_gcm_x86.c:vu_ror_variable	0
fd_aes_gcm_x86.c:vu_ror_vector	0
fd_aes_gcm_x86.c:vu_st	0
fd_aes_gcm_x86.c:vu_stu	0
fd_aes_gcm_x86.c:vu_sum_all	0
fd_aes_gcm_x86.c:vu_to_vd_core	0
fd_aes_gcm_x86.c:vu_to_vf	0
fd_chacha20_sse.c:vu_bcast_pair	0
fd_chacha20_sse.c:vu_bcast_wide	0
fd_chacha20_sse.c:vu_extract_variable	0
fd_chacha20_sse.c:vu_gather	0
fd_chacha20_sse.c:vu_insert_variable	0
fd_chacha20_sse.c:vu_ldu	0
fd_chacha20_sse.c:vu_max_all	0
fd_chacha20_sse.c:vu_min_all	0
fd_chacha20_sse.c:vu_rol_variable	0
fd_chacha20_sse.c:vu_rol_vector	0
fd_chacha20_sse.c:vu_ror	0
fd_chacha20_sse.c:vu_ror_variable	0
fd_chacha20_sse.c:vu_ror_vector	0
fd_chacha20_sse.c:vu_stu	0
fd_chacha20_sse.c:vu_sum_all	0
fd_chacha20_sse.c:vu_to_vd_core	0
fd_chacha20_sse.c:vu_to_vf	0
fd_dbl_buf.c:vu_bcast_pair	0
fd_dbl_buf.c:vu_bcast_wide	0
fd_dbl_buf.c:vu_extract_variable	0
fd_dbl_buf.c:vu_gather	0
fd_dbl_buf.c:vu_insert_variable	0
fd_dbl_buf.c:vu_ld	0
fd_dbl_buf.c:vu_ldu	0
fd_dbl_buf.c:vu_max_all	0
fd_dbl_buf.c:vu_min_all	0
fd_dbl_buf.c:vu_rol	0
fd_dbl_buf.c:vu_rol_variable	0
fd_dbl_buf.c:vu_rol_vector	0
fd_dbl_buf.c:vu_ror	0
fd_dbl_buf.c:vu_ror_variable	0
fd_dbl_buf.c:vu_ror_vector	0
fd_dbl_buf.c:vu_st	0
fd_dbl_buf.c:vu_stu	0
fd_dbl_buf.c:vu_sum_all	0
fd_dbl_buf.c:vu_to_vd_core	0
fd_dbl_buf.c:vu_to_vf	0
fd_reedsol_pi.c:vu_bcast_pair	0
fd_reedsol_pi.c:vu_bcast_wide	0
fd_reedsol_pi.c:vu_extract_variable	0
fd_reedsol_pi.c:vu_gather	0
fd_reedsol_pi.c:vu_insert_variable	0
fd_reedsol_pi.c:vu_ld	0
fd_reedsol_pi.c:vu_ldu	0
fd_reedsol_pi.c:vu_max_all	0
fd_reedsol_pi.c:vu_min_all	0
fd_reedsol_pi.c:vu_rol	0
fd_reedsol_pi.c:vu_rol_variable	0
fd_reedsol_pi.c:vu_rol_vector	0
fd_reedsol_pi.c:vu_ror	0
fd_reedsol_pi.c:vu_ror_variable	0
fd_reedsol_pi.c:vu_ror_vector	0
fd_reedsol_pi.c:vu_st	0
fd_reedsol_pi.c:vu_stu	0
fd_reedsol_pi.c:vu_sum_all	0
fd_reedsol_pi.c:vu_to_vd_core	0
fd_reedsol_pi.c:vu_to_vf	0
fd_sha256.c:vu_bcast_pair	0
fd_sha256.c:vu_bcast_wide	0
fd_sha256.c:vu_extract_variable	0
fd_sha256.c:vu_gather	0
fd_sha256.c:vu_insert_variable	0
fd_sha256.c:vu_max_all	0
fd_sha256.c:vu_min_all	0
fd_sha256.c:vu_rol_variable	0
fd_sha256.c:vu_rol_vector	0
fd_sha256.c:vu_ror_variable	0
fd_sha256.c:vu_ror_vector	0
fd_sha256.c:vu_sum_all	0
fd_sha256.c:vu_to_vd_core	0
fd_sha256.c:vu_to_vf	0
test_sse_16x8.c:vu_bcast_pair	0
test_sse_16x8.c:vu_bcast_wide	0
test_sse_16x8.c:vu_extract_variable	0
test_sse_16x8.c:vu_gather	0
test_sse_16x8.c:vu_insert_variable	0
test_sse_16x8.c:vu_ld	0
test_sse_16x8.c:vu_ldu	0
test_sse_16x8.c:vu_max_all	0
test_sse_16x8.c:vu_min_all	0
test_sse_16x8.c:vu_rol	0
test_sse_16x8.c:vu_rol_variable	0
test_sse_16x8.c:vu_rol_vector	0
test_sse_16x8.c:vu_ror	0
test_sse_16x8.c:vu_ror_variable	0
test_sse_16x8.c:vu_ror_vector	0
test_sse_16x8.c:vu_st	0
test_sse_16x8.c:vu_stu	0
test_sse_16x8.c:vu_sum_all	0
test_sse_16x8.c:vu_to_vd_core	0
test_sse_16x8.c:vu_to_vf	0
test_sse_2x64.c:vu_bcast_pair	0
test_sse_2x64.c:vu_bcast_wide	0
test_sse_2x64.c:vu_extract_variable	0
test_sse_2x64.c:vu_gather	0
test_sse_2x64.c:vu_insert_variable	0
test_sse_2x64.c:vu_ld	0
test_sse_2x64.c:vu_ldu	0
test_sse_2x64.c:vu_max_all	0
test_sse_2x64.c:vu_min_all	0
test_sse_2x64.c:vu_rol	0
test_sse_2x64.c:vu_rol_variable	0
test_sse_2x64.c:vu_rol_vector	0
test_sse_2x64.c:vu_ror	0
test_sse_2x64.c:vu_ror_variable	0
test_sse_2x64.c:vu_ror_vector	0
test_sse_2x64.c:vu_st	0
test_sse_2x64.c:vu_stu	0
test_sse_2x64.c:vu_sum_all	0
test_sse_2x64.c:vu_to_vd_core	0
test_sse_2x64.c:vu_to_vf	0
test_sse_4x32.c:vu_extract_variable	0
test_sse_4x32.c:vu_gather	0
test_sse_4x32.c:vu_insert_variable	0
test_sse_4x32.c:vu_ld	0
test_sse_4x32.c:vu_ldu	0
test_sse_4x32.c:vu_rol_vector	0
test_sse_4x32.c:vu_ror_vector	0
test_sse_4x32.c:vu_st	0
test_sse_4x32.c:vu_stu	0
test_sse_common.c:vu_bcast_pair	0
test_sse_common.c:vu_bcast_wide	0
test_sse_common.c:vu_max_all	0
test_sse_common.c:vu_min_all	0
test_sse_common.c:vu_rol	0
test_sse_common.c:vu_rol_variable	0
test_sse_common.c:vu_rol_vector	0
test_sse_common.c:vu_ror	0
test_sse_common.c:vu_ror_variable	0
test_sse_common.c:vu_ror_vector	0
test_sse_common.c:vu_sum_all	0
test_sse_common.c:vu_to_vd_core	0
test_sse_common.c:vu_to_vf	0
test_sse_4x32.c:vu_bcast_pair	196608
test_sse_4x32.c:vu_bcast_wide	196608
test_sse_4x32.c:vu_max_all	196608
test_sse_4x32.c:vu_min_all	196608
test_sse_4x32.c:vu_sum_all	196608
test_sse_4x32.c:vu_to_vf	196608
fd_sha256.c:vu_stu	202066
test_sse_4x32.c:vu_to_vd_core	3538944
test_sse_4x32.c:vu_rol	4194304
test_sse_4x32.c:vu_ror	4194304
test_sse_4x32.c:vu_rol_variable	6291456
test_sse_4x32.c:vu_ror_variable	6291456
test_sse_common.c:vu_gather	61538355
test_sse_common.c:vu_ld	61538355
test_sse_common.c:vu_st	61538355
fd_chacha20_sse.c:vu_ld	99000009
fd_chacha20_sse.c:vu_st	132000012
fd_sha256.c:vu_st	211708588
test_sse_common.c:vu_extract_variable	246153420
test_sse_common.c:vu_insert_variable	246153420
test_sse_common.c:vu_ldu	246153420
test_sse_common.c:vu_stu	246153420
fd_sha256.c:vu_ldu	750571738
fd_chacha20_sse.c:vu_rol	880000080
fd_sha256.c:vu_ld	5178006460

Generated by: LCOV version 1.14