LCOV - code coverage report

Current view: top level - waltz/tls - test_tls_helper.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 63 70 90.0 % Date: 2024-11-14 11:55:10 Functions: 14 189 7.4 %

Function Name	Hit count
fd_benchs.c:fd_tls_test_rand	0
fd_benchs.c:fd_tls_test_rand_read	0
fd_benchs.c:fd_tls_test_sign	0
fd_benchs.c:fd_tls_test_sign_ctx	0
fd_benchs.c:fd_tls_test_sign_sign	0
fd_benchs.c:test_record_log	0
fd_benchs.c:test_record_recv	0
fd_benchs.c:test_record_reset	0
fd_benchs.c:test_record_send	0
fd_quic_test_helpers.c:fd_tls_test_rand	0
fd_quic_test_helpers.c:fd_tls_test_rand_read	0
fd_quic_test_helpers.c:fd_tls_test_sign	0
fd_quic_test_helpers.c:test_record_log	0
fd_quic_test_helpers.c:test_record_recv	0
fd_quic_test_helpers.c:test_record_reset	0
fd_quic_test_helpers.c:test_record_send	0
fuzz_quic.c:fd_tls_test_rand	0
fuzz_quic.c:fd_tls_test_rand_read	0
fuzz_quic.c:fd_tls_test_sign	0
fuzz_quic.c:fd_tls_test_sign_ctx	0
fuzz_quic.c:fd_tls_test_sign_sign	0
fuzz_quic.c:test_record_log	0
fuzz_quic.c:test_record_recv	0
fuzz_quic.c:test_record_reset	0
fuzz_quic.c:test_record_send	0
fuzz_quic_wire.c:fd_tls_test_rand	0
fuzz_quic_wire.c:fd_tls_test_rand_read	0
fuzz_quic_wire.c:fd_tls_test_sign	0
fuzz_quic_wire.c:fd_tls_test_sign_sign	0
fuzz_quic_wire.c:test_record_log	0
fuzz_quic_wire.c:test_record_recv	0
fuzz_quic_wire.c:test_record_reset	0
fuzz_quic_wire.c:test_record_send	0
fuzz_tls.c:fd_tls_test_rand	0
fuzz_tls.c:fd_tls_test_rand_read	0
fuzz_tls.c:fd_tls_test_sign	0
fuzz_tls.c:fd_tls_test_sign_ctx	0
fuzz_tls.c:fd_tls_test_sign_sign	0
fuzz_tls.c:test_record_log	0
fuzz_tls.c:test_record_recv	0
fuzz_tls.c:test_record_reset	0
fuzz_tls.c:test_record_send	0
test_quic_arp_client.c:fd_tls_test_rand	0
test_quic_arp_client.c:fd_tls_test_rand_read	0
test_quic_arp_client.c:fd_tls_test_sign	0
test_quic_arp_client.c:fd_tls_test_sign_ctx	0
test_quic_arp_client.c:fd_tls_test_sign_sign	0
test_quic_arp_client.c:test_record_log	0
test_quic_arp_client.c:test_record_recv	0
test_quic_arp_client.c:test_record_reset	0
test_quic_arp_client.c:test_record_send	0
test_quic_arp_server.c:fd_tls_test_rand	0
test_quic_arp_server.c:fd_tls_test_rand_read	0
test_quic_arp_server.c:fd_tls_test_sign	0
test_quic_arp_server.c:fd_tls_test_sign_ctx	0
test_quic_arp_server.c:fd_tls_test_sign_sign	0
test_quic_arp_server.c:test_record_log	0
test_quic_arp_server.c:test_record_recv	0
test_quic_arp_server.c:test_record_reset	0
test_quic_arp_server.c:test_record_send	0
test_quic_bw.c:fd_tls_test_rand	0
test_quic_bw.c:fd_tls_test_rand_read	0
test_quic_bw.c:fd_tls_test_sign	0
test_quic_bw.c:fd_tls_test_sign_ctx	0
test_quic_bw.c:fd_tls_test_sign_sign	0
test_quic_bw.c:test_record_log	0
test_quic_bw.c:test_record_recv	0
test_quic_bw.c:test_record_reset	0
test_quic_bw.c:test_record_send	0
test_quic_client_flood.c:fd_tls_test_rand	0
test_quic_client_flood.c:fd_tls_test_rand_read	0
test_quic_client_flood.c:fd_tls_test_sign	0
test_quic_client_flood.c:fd_tls_test_sign_ctx	0
test_quic_client_flood.c:fd_tls_test_sign_sign	0
test_quic_client_flood.c:test_record_log	0
test_quic_client_flood.c:test_record_recv	0
test_quic_client_flood.c:test_record_reset	0
test_quic_client_flood.c:test_record_send	0
test_quic_conn.c:fd_tls_test_rand	0
test_quic_conn.c:fd_tls_test_rand_read	0
test_quic_conn.c:fd_tls_test_sign	0
test_quic_conn.c:fd_tls_test_sign_ctx	0
test_quic_conn.c:fd_tls_test_sign_sign	0
test_quic_conn.c:test_record_log	0
test_quic_conn.c:test_record_recv	0
test_quic_conn.c:test_record_reset	0
test_quic_conn.c:test_record_send	0
test_quic_drops.c:fd_tls_test_rand	0
test_quic_drops.c:fd_tls_test_rand_read	0
test_quic_drops.c:fd_tls_test_sign	0
test_quic_drops.c:fd_tls_test_sign_ctx	0
test_quic_drops.c:fd_tls_test_sign_sign	0
test_quic_drops.c:test_record_log	0
test_quic_drops.c:test_record_recv	0
test_quic_drops.c:test_record_reset	0
test_quic_drops.c:test_record_send	0
test_quic_hs.c:fd_tls_test_rand	0
test_quic_hs.c:fd_tls_test_rand_read	0
test_quic_hs.c:fd_tls_test_sign	0
test_quic_hs.c:fd_tls_test_sign_ctx	0
test_quic_hs.c:fd_tls_test_sign_sign	0
test_quic_hs.c:test_record_log	0
test_quic_hs.c:test_record_recv	0
test_quic_hs.c:test_record_reset	0
test_quic_hs.c:test_record_send	0
test_quic_idle_conns.c:fd_tls_test_rand	0
test_quic_idle_conns.c:fd_tls_test_rand_read	0
test_quic_idle_conns.c:fd_tls_test_sign	0
test_quic_idle_conns.c:fd_tls_test_sign_ctx	0
test_quic_idle_conns.c:fd_tls_test_sign_sign	0
test_quic_idle_conns.c:test_record_log	0
test_quic_idle_conns.c:test_record_recv	0
test_quic_idle_conns.c:test_record_reset	0
test_quic_idle_conns.c:test_record_send	0
test_quic_key_phase.c:fd_tls_test_rand	0
test_quic_key_phase.c:fd_tls_test_rand_read	0
test_quic_key_phase.c:fd_tls_test_sign	0
test_quic_key_phase.c:fd_tls_test_sign_ctx	0
test_quic_key_phase.c:fd_tls_test_sign_sign	0
test_quic_key_phase.c:test_record_log	0
test_quic_key_phase.c:test_record_recv	0
test_quic_key_phase.c:test_record_reset	0
test_quic_key_phase.c:test_record_send	0
test_quic_retry_integration.c:fd_tls_test_rand	0
test_quic_retry_integration.c:fd_tls_test_rand_read	0
test_quic_retry_integration.c:fd_tls_test_sign	0
test_quic_retry_integration.c:fd_tls_test_sign_ctx	0
test_quic_retry_integration.c:fd_tls_test_sign_sign	0
test_quic_retry_integration.c:test_record_log	0
test_quic_retry_integration.c:test_record_recv	0
test_quic_retry_integration.c:test_record_reset	0
test_quic_retry_integration.c:test_record_send	0
test_quic_server.c:fd_tls_test_rand	0
test_quic_server.c:fd_tls_test_rand_read	0
test_quic_server.c:fd_tls_test_sign	0
test_quic_server.c:fd_tls_test_sign_ctx	0
test_quic_server.c:fd_tls_test_sign_sign	0
test_quic_server.c:test_record_log	0
test_quic_server.c:test_record_recv	0
test_quic_server.c:test_record_reset	0
test_quic_server.c:test_record_send	0
test_quic_streams.c:fd_tls_test_rand	0
test_quic_streams.c:fd_tls_test_rand_read	0
test_quic_streams.c:fd_tls_test_sign	0
test_quic_streams.c:fd_tls_test_sign_ctx	0
test_quic_streams.c:fd_tls_test_sign_sign	0
test_quic_streams.c:test_record_log	0
test_quic_streams.c:test_record_recv	0
test_quic_streams.c:test_record_reset	0
test_quic_streams.c:test_record_send	0
test_quic_tls_hs.c:fd_tls_test_rand	0
test_quic_tls_hs.c:fd_tls_test_rand_read	0
test_quic_tls_hs.c:test_record_log	0
test_quic_tls_hs.c:test_record_recv	0
test_quic_tls_hs.c:test_record_reset	0
test_quic_tls_hs.c:test_record_send	0
test_quic_txns.c:fd_tls_test_rand	0
test_quic_txns.c:fd_tls_test_rand_read	0
test_quic_txns.c:fd_tls_test_sign	0
test_quic_txns.c:fd_tls_test_sign_ctx	0
test_quic_txns.c:fd_tls_test_sign_sign	0
test_quic_txns.c:test_record_log	0
test_quic_txns.c:test_record_recv	0
test_quic_txns.c:test_record_reset	0
test_quic_txns.c:test_record_send	0
test_tls.c:test_record_reset	0
txn.c:fd_tls_test_rand	0
txn.c:fd_tls_test_rand_read	0
txn.c:fd_tls_test_sign	0
txn.c:fd_tls_test_sign_ctx	0
txn.c:fd_tls_test_sign_sign	0
txn.c:test_record_log	0
txn.c:test_record_recv	0
txn.c:test_record_reset	0
txn.c:test_record_send	0
test_quic_tls_hs.c:fd_tls_test_sign	3
test_quic_tls_hs.c:fd_tls_test_sign_ctx	3
test_quic_tls_hs.c:fd_tls_test_sign_sign	3
test_tls.c:fd_tls_test_sign_sign	3
test_tls.c:fd_tls_test_rand_read	9
test_tls.c:fd_tls_test_rand	18
test_tls.c:fd_tls_test_sign	18
test_tls.c:fd_tls_test_sign_ctx	18
test_tls.c:test_record_log	24
test_tls.c:test_record_send	24
test_tls.c:test_record_recv	30
fd_quic_test_helpers.c:fd_tls_test_sign_ctx	33
fuzz_quic_wire.c:fd_tls_test_sign_ctx	2088
fd_quic_test_helpers.c:fd_tls_test_sign_sign	6012

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