LCOV - code coverage report

Current view: top level - waltz/tls - test_tls_helper.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 58 61 95.1 % Date: 2026-09-17 04:28:31 Functions: 18 200 9.0 %

Function Name	Hit count
fd_benchs.c:fd_tls_test_rand	0
fd_benchs.c:fd_tls_test_sign	0
fd_benchs.c:fd_tls_test_sign_ctx	0
fd_benchs.c:fd_tls_test_sign_sign	0
fd_benchs.c:test_record_log	0
fd_benchs.c:test_record_recv	0
fd_benchs.c:test_record_reset	0
fd_benchs.c:test_record_send	0
fd_quic_test_helpers.c:fd_tls_test_rand	0
fd_quic_test_helpers.c:fd_tls_test_sign	0
fd_quic_test_helpers.c:fd_tls_test_sign_ctx	48
fd_quic_test_helpers.c:fd_tls_test_sign_sign	12138
fd_quic_test_helpers.c:test_record_log	0
fd_quic_test_helpers.c:test_record_recv	0
fd_quic_test_helpers.c:test_record_reset	0
fd_quic_test_helpers.c:test_record_send	0
fuzz_quic.c:fd_tls_test_rand	0
fuzz_quic.c:fd_tls_test_sign	0
fuzz_quic.c:fd_tls_test_sign_ctx	0
fuzz_quic.c:fd_tls_test_sign_sign	0
fuzz_quic.c:test_record_log	0
fuzz_quic.c:test_record_recv	0
fuzz_quic.c:test_record_reset	0
fuzz_quic.c:test_record_send	0
fuzz_quic_actor.c:fd_tls_test_rand	0
fuzz_quic_actor.c:fd_tls_test_sign	0
fuzz_quic_actor.c:fd_tls_test_sign_ctx	0
fuzz_quic_actor.c:fd_tls_test_sign_sign	0
fuzz_quic_actor.c:test_record_log	0
fuzz_quic_actor.c:test_record_recv	0
fuzz_quic_actor.c:test_record_reset	0
fuzz_quic_actor.c:test_record_send	0
fuzz_quic_wire.c:fd_tls_test_rand	0
fuzz_quic_wire.c:fd_tls_test_sign	0
fuzz_quic_wire.c:fd_tls_test_sign_ctx	0
fuzz_quic_wire.c:fd_tls_test_sign_sign	0
fuzz_quic_wire.c:test_record_log	0
fuzz_quic_wire.c:test_record_recv	0
fuzz_quic_wire.c:test_record_reset	0
fuzz_quic_wire.c:test_record_send	0
fuzz_tls.c:fd_tls_test_rand	0
fuzz_tls.c:fd_tls_test_sign	0
fuzz_tls.c:fd_tls_test_sign_ctx	0
fuzz_tls.c:fd_tls_test_sign_sign	0
fuzz_tls.c:test_record_log	0
fuzz_tls.c:test_record_recv	0
fuzz_tls.c:test_record_reset	0
fuzz_tls.c:test_record_send	0
fuzz_tlsrec.c:fd_tls_test_rand	0
fuzz_tlsrec.c:fd_tls_test_sign	0
fuzz_tlsrec.c:fd_tls_test_sign_ctx	0
fuzz_tlsrec.c:fd_tls_test_sign_sign	0
fuzz_tlsrec.c:test_record_log	0
fuzz_tlsrec.c:test_record_recv	0
fuzz_tlsrec.c:test_record_reset	0
fuzz_tlsrec.c:test_record_send	0
test_event_client.c:fd_tls_test_rand	0
test_event_client.c:fd_tls_test_sign	0
test_event_client.c:fd_tls_test_sign_ctx	0
test_event_client.c:fd_tls_test_sign_sign	0
test_event_client.c:test_record_log	0
test_event_client.c:test_record_recv	0
test_event_client.c:test_record_reset	0
test_event_client.c:test_record_send	0
test_quic_bw.c:fd_tls_test_rand	0
test_quic_bw.c:fd_tls_test_sign	0
test_quic_bw.c:fd_tls_test_sign_ctx	0
test_quic_bw.c:fd_tls_test_sign_sign	0
test_quic_bw.c:test_record_log	0
test_quic_bw.c:test_record_recv	0
test_quic_bw.c:test_record_reset	0
test_quic_bw.c:test_record_send	0
test_quic_client_flood.c:fd_tls_test_rand	0
test_quic_client_flood.c:fd_tls_test_sign	0
test_quic_client_flood.c:fd_tls_test_sign_ctx	0
test_quic_client_flood.c:fd_tls_test_sign_sign	0
test_quic_client_flood.c:test_record_log	0
test_quic_client_flood.c:test_record_recv	0
test_quic_client_flood.c:test_record_reset	0
test_quic_client_flood.c:test_record_send	0
test_quic_conn.c:fd_tls_test_rand	0
test_quic_conn.c:fd_tls_test_sign	0
test_quic_conn.c:fd_tls_test_sign_ctx	0
test_quic_conn.c:fd_tls_test_sign_sign	0
test_quic_conn.c:test_record_log	0
test_quic_conn.c:test_record_recv	0
test_quic_conn.c:test_record_reset	0
test_quic_conn.c:test_record_send	0
test_quic_hs.c:fd_tls_test_rand	0
test_quic_hs.c:fd_tls_test_sign	0
test_quic_hs.c:fd_tls_test_sign_ctx	0
test_quic_hs.c:fd_tls_test_sign_sign	0
test_quic_hs.c:test_record_log	0
test_quic_hs.c:test_record_recv	0
test_quic_hs.c:test_record_reset	0
test_quic_hs.c:test_record_send	0
test_quic_idle_conns.c:fd_tls_test_rand	0
test_quic_idle_conns.c:fd_tls_test_sign	0
test_quic_idle_conns.c:fd_tls_test_sign_ctx	0
test_quic_idle_conns.c:fd_tls_test_sign_sign	0
test_quic_idle_conns.c:test_record_log	0
test_quic_idle_conns.c:test_record_recv	0
test_quic_idle_conns.c:test_record_reset	0
test_quic_idle_conns.c:test_record_send	0
test_quic_keep_alive.c:fd_tls_test_rand	0
test_quic_keep_alive.c:fd_tls_test_sign	0
test_quic_keep_alive.c:fd_tls_test_sign_ctx	0
test_quic_keep_alive.c:fd_tls_test_sign_sign	0
test_quic_keep_alive.c:test_record_log	0
test_quic_keep_alive.c:test_record_recv	0
test_quic_keep_alive.c:test_record_reset	0
test_quic_keep_alive.c:test_record_send	0
test_quic_key_phase.c:fd_tls_test_rand	0
test_quic_key_phase.c:fd_tls_test_sign	0
test_quic_key_phase.c:fd_tls_test_sign_ctx	0
test_quic_key_phase.c:fd_tls_test_sign_sign	0
test_quic_key_phase.c:test_record_log	0
test_quic_key_phase.c:test_record_recv	0
test_quic_key_phase.c:test_record_reset	0
test_quic_key_phase.c:test_record_send	0
test_quic_pkt_meta.c:fd_tls_test_rand	0
test_quic_pkt_meta.c:fd_tls_test_sign	0
test_quic_pkt_meta.c:fd_tls_test_sign_ctx	0
test_quic_pkt_meta.c:fd_tls_test_sign_sign	0
test_quic_pkt_meta.c:test_record_log	0
test_quic_pkt_meta.c:test_record_recv	0
test_quic_pkt_meta.c:test_record_reset	0
test_quic_pkt_meta.c:test_record_send	0
test_quic_retry_integration.c:fd_tls_test_rand	0
test_quic_retry_integration.c:fd_tls_test_sign	0
test_quic_retry_integration.c:fd_tls_test_sign_ctx	0
test_quic_retry_integration.c:fd_tls_test_sign_sign	0
test_quic_retry_integration.c:test_record_log	0
test_quic_retry_integration.c:test_record_recv	0
test_quic_retry_integration.c:test_record_reset	0
test_quic_retry_integration.c:test_record_send	0
test_quic_retx.c:fd_tls_test_rand	0
test_quic_retx.c:fd_tls_test_sign	0
test_quic_retx.c:fd_tls_test_sign_ctx	0
test_quic_retx.c:fd_tls_test_sign_sign	0
test_quic_retx.c:test_record_log	0
test_quic_retx.c:test_record_recv	0
test_quic_retx.c:test_record_reset	0
test_quic_retx.c:test_record_send	0
test_quic_server.c:fd_tls_test_rand	0
test_quic_server.c:fd_tls_test_sign	0
test_quic_server.c:fd_tls_test_sign_ctx	0
test_quic_server.c:fd_tls_test_sign_sign	0
test_quic_server.c:test_record_log	0
test_quic_server.c:test_record_recv	0
test_quic_server.c:test_record_reset	0
test_quic_server.c:test_record_send	0
test_quic_streams.c:fd_tls_test_rand	0
test_quic_streams.c:fd_tls_test_sign	0
test_quic_streams.c:fd_tls_test_sign_ctx	0
test_quic_streams.c:fd_tls_test_sign_sign	0
test_quic_streams.c:test_record_log	0
test_quic_streams.c:test_record_recv	0
test_quic_streams.c:test_record_reset	0
test_quic_streams.c:test_record_send	0
test_quic_tls_hs.c:fd_tls_test_rand	3
test_quic_tls_hs.c:fd_tls_test_sign	3
test_quic_tls_hs.c:fd_tls_test_sign_ctx	3
test_quic_tls_hs.c:fd_tls_test_sign_sign	6
test_quic_tls_hs.c:test_record_log	0
test_quic_tls_hs.c:test_record_recv	0
test_quic_tls_hs.c:test_record_reset	0
test_quic_tls_hs.c:test_record_send	0
test_quic_txns.c:fd_tls_test_rand	0
test_quic_txns.c:fd_tls_test_sign	0
test_quic_txns.c:fd_tls_test_sign_ctx	0
test_quic_txns.c:fd_tls_test_sign_sign	0
test_quic_txns.c:test_record_log	0
test_quic_txns.c:test_record_recv	0
test_quic_txns.c:test_record_reset	0
test_quic_txns.c:test_record_send	0
test_tls.c:fd_tls_test_rand	120
test_tls.c:fd_tls_test_sign	120
test_tls.c:fd_tls_test_sign_ctx	120
test_tls.c:fd_tls_test_sign_sign	9
test_tls.c:test_record_log	60
test_tls.c:test_record_recv	57
test_tls.c:test_record_reset	24
test_tls.c:test_record_send	60
test_tlsrec.c:fd_tls_test_rand	45
test_tlsrec.c:fd_tls_test_sign	42
test_tlsrec.c:fd_tls_test_sign_ctx	42
test_tlsrec.c:fd_tls_test_sign_sign	378
test_tlsrec.c:test_record_log	0
test_tlsrec.c:test_record_recv	0
test_tlsrec.c:test_record_reset	0
test_tlsrec.c:test_record_send	0
txn.c:fd_tls_test_rand	0
txn.c:fd_tls_test_sign	0
txn.c:fd_tls_test_sign_ctx	0
txn.c:fd_tls_test_sign_sign	0
txn.c:test_record_log	0
txn.c:test_record_recv	0
txn.c:test_record_reset	0
txn.c:test_record_send	0

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